Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Modified from arch/mips/pnx833x/common/prom.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/serial_reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/fw/fw.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <loongson1.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) unsigned long memsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) void __init prom_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	void __iomem *uart_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	fw_init_cmdline();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	memsize = fw_getenvl("memsize");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	if(!memsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		memsize = DEFAULT_MEMSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	if (strstr(arcs_cmdline, "console=ttyS3"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		uart_base = ioremap(LS1X_UART3_BASE, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	else if (strstr(arcs_cmdline, "console=ttyS2"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		uart_base = ioremap(LS1X_UART2_BASE, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	else if (strstr(arcs_cmdline, "console=ttyS1"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		uart_base = ioremap(LS1X_UART1_BASE, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		uart_base = ioremap(LS1X_UART0_BASE, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	setup_8250_early_printk_port((unsigned long)uart_base, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) void __init prom_free_prom_memory(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) void __init plat_mem_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	memblock_add(0x0, (memsize << 20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }