Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * Copyright (C) 2006 - 2008 Lemote Inc. & Institute of Computing Technology
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Author: Yanhua, yanh@lemote.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/mach-loongson2ef/loongson.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	DC_ZERO, DC_25PT = 2, DC_37PT, DC_50PT, DC_62PT, DC_75PT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	DC_87PT, DC_DISABLE, DC_RESV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct cpufreq_frequency_table loongson2_clockmod_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	{0, DC_RESV, CPUFREQ_ENTRY_INVALID},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	{0, DC_ZERO, CPUFREQ_ENTRY_INVALID},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	{0, DC_25PT, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	{0, DC_37PT, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	{0, DC_50PT, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	{0, DC_62PT, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	{0, DC_75PT, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	{0, DC_87PT, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	{0, DC_DISABLE, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	{0, DC_RESV, CPUFREQ_TABLE_END},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) EXPORT_SYMBOL_GPL(loongson2_clockmod_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int loongson2_cpu_set_rate(unsigned long rate_khz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	struct cpufreq_frequency_table *pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	cpufreq_for_each_valid_entry(pos, loongson2_clockmod_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		if (rate_khz == pos->frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	if (rate_khz != pos->frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	regval = readl(LOONGSON_CHIPCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	regval = (regval & ~0x7) | (pos->driver_data - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	writel(regval, LOONGSON_CHIPCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) EXPORT_SYMBOL_GPL(loongson2_cpu_set_rate);