^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * loongson-specific suspend support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009 Lemote Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Wu Zhangjin <wuzhangjin@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/i8259.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <loongson.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static unsigned int __maybe_unused cached_master_mask; /* i8259A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static unsigned int __maybe_unused cached_slave_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static unsigned int __maybe_unused cached_bonito_irq_mask; /* bonito */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) void arch_suspend_disable_irqs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* disable all mips events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #ifdef CONFIG_I8259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* disable all events of i8259A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) cached_slave_mask = inb(PIC_SLAVE_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) cached_master_mask = inb(PIC_MASTER_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) outb(0xff, PIC_SLAVE_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) inb(PIC_SLAVE_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) outb(0xff, PIC_MASTER_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) inb(PIC_MASTER_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* disable all events of bonito */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) cached_bonito_irq_mask = LOONGSON_INTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) LOONGSON_INTENCLR = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) (void)LOONGSON_INTENCLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void arch_suspend_enable_irqs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* enable all mips events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) local_irq_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #ifdef CONFIG_I8259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* only enable the cached events of i8259A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) outb(cached_slave_mask, PIC_SLAVE_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) outb(cached_master_mask, PIC_MASTER_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* enable all cached events of bonito */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) LOONGSON_INTENSET = cached_bonito_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) (void)LOONGSON_INTENSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * Setup the board-specific events for waking up loongson from wait mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) void __weak setup_wakeup_events(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Check wakeup events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int __weak wakeup_loongson(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * If the events are really what we want to wakeup the CPU, wake it up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * otherwise put the CPU asleep again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static void wait_for_wakeup_events(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) while (!wakeup_loongson())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) writel(readl(LOONGSON_CHIPCFG) & ~0x7, LOONGSON_CHIPCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * Stop all perf counters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * $24 is the control register of Loongson perf counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static inline void stop_perf_counters(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) __write_64bit_c0_register($24, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void loongson_suspend_enter(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned int cached_cpu_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* setup wakeup events via enabling the IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) setup_wakeup_events();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) stop_perf_counters();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) cached_cpu_freq = readl(LOONGSON_CHIPCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Put CPU into wait mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) writel(readl(LOONGSON_CHIPCFG) & ~0x7, LOONGSON_CHIPCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* wait for the given events to wakeup cpu from wait mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) wait_for_wakeup_events();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) writel(cached_cpu_freq, LOONGSON_CHIPCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) mmiowb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) void __weak mach_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) void __weak mach_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int loongson_pm_enter(suspend_state_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) mach_suspend();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* processor specific suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) loongson_suspend_enter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) mach_resume();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int loongson_pm_valid_state(suspend_state_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) case PM_SUSPEND_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) case PM_SUSPEND_STANDBY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) case PM_SUSPEND_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const struct platform_suspend_ops loongson_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .valid = loongson_pm_valid_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .enter = loongson_pm_enter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int __init loongson_pm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) suspend_set_ops(&loongson_pm_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) arch_initcall(loongson_pm_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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