Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2007 Lemote Inc. & Institute of Computing Technology
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Author: Fuxin Zhang, zhangfx@lemote.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <loongson.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * the first level int-handler will jump here if it is a bonito irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) void bonito_irqdispatch(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	u32 int_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	/* workaround the IO dma problem: let cpu looping to allow DMA finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	int_status = LOONGSON_INTISR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	while (int_status & (1 << 10)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		int_status = LOONGSON_INTISR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	/* Get pending sources, masked by current enables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	int_status = LOONGSON_INTISR & LOONGSON_INTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	if (int_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		i = __ffs(int_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		do_IRQ(LOONGSON_IRQ_BASE + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) asmlinkage void plat_irq_dispatch(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	unsigned int pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	pending = read_c0_cause() & read_c0_status() & ST0_IM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	/* machine-specific plat_irq_dispatch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	mach_irq_dispatch(pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) void __init arch_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	 * Clear all of the interrupts while we change the able around a bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	 * int-handler is not on bootstrap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	clear_c0_status(ST0_IM | ST0_BEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	/* no steer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	LOONGSON_INTSTEER = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	 * Mask out all interrupt by writing "1" to all bit position in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	 * the interrupt reset reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	LOONGSON_INTENCLR = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	/* machine specific irq init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	mach_init_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }