^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2011-2012 John Crispin <john@phrozen.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <lantiq_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "../clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "../prom.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* clock control register for legacy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CGU_IFCCR 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CGU_IFCCR_VR9 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* system clock register for legacy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CGU_SYS 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* pci control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CGU_PCICR 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CGU_PCICR_VR9 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* ephy configuration register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CGU_EPHY 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Legacy PMU register for ar9, ase, danube */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* power control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PMU_PWDCR 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* power status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PMU_PWDSR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* power control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PMU_PWDCR1 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* power status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PMU_PWDSR1 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* power control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PWDCR(x) ((x) ? (PMU_PWDCR1) : (PMU_PWDCR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* power status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* PMU register for ar10 and grx390 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* First register set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PMU_CLK_SR 0x20 /* status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PMU_CLK_CR_A 0x24 /* Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PMU_CLK_CR_B 0x28 /* Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Second register set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PMU_CLK_SR1 0x30 /* status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PMU_CLK_CR1_A 0x34 /* Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PMU_CLK_CR1_B 0x38 /* Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Third register set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PMU_ANA_SR 0x40 /* status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PMU_ANA_CR_A 0x44 /* Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PMU_ANA_CR_B 0x48 /* Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static u32 pmu_clk_sr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PMU_CLK_SR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PMU_CLK_SR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PMU_ANA_SR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static u32 pmu_clk_cr_a[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) PMU_CLK_CR_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) PMU_CLK_CR1_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) PMU_ANA_CR_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static u32 pmu_clk_cr_b[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) PMU_CLK_CR_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) PMU_CLK_CR1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) PMU_ANA_CR_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PWDCR_EN_XRX(x) (pmu_clk_cr_a[(x)])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PWDCR_DIS_XRX(x) (pmu_clk_cr_b[(x)])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PWDSR_XRX(x) (pmu_clk_sr[(x)])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* clock gates that we can en/disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PMU_USB0_P BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PMU_ASE_SDIO BIT(2) /* ASE special */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PMU_PCI BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PMU_DMA BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PMU_USB0 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PMU_ASC0 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PMU_EPHY BIT(7) /* ase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PMU_USIF BIT(7) /* from vr9 until grx390 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PMU_SPI BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PMU_DFE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PMU_EBU BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PMU_STP BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PMU_GPT BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PMU_AHBS BIT(13) /* vr9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PMU_FPI BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PMU_AHBM BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PMU_SDIO BIT(16) /* danube, ar9, vr9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PMU_ASC1 BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PMU_PPE_QSB BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PMU_PPE_SLL01 BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PMU_DEU BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PMU_PPE_TC BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PMU_PPE_EMA BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PMU_PPE_DPLUM BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PMU_PPE_DP BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PMU_PPE_DPLUS BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PMU_USB1_P BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PMU_GPHY3 BIT(26) /* grx390 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PMU_USB1 BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PMU_SWITCH BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PMU_PPE_TOP BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PMU_GPHY0 BIT(29) /* ar10, xrx390 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PMU_GPHY BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PMU_GPHY1 BIT(30) /* ar10, xrx390 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PMU_PCIE_CLK BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PMU_GPHY2 BIT(31) /* ar10, xrx390 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PMU1_PCIE_PHY BIT(0) /* vr9-specific,moved in ar10/grx390 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PMU1_PCIE_CTL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PMU1_PCIE_PDI BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PMU1_PCIE_MSI BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PMU1_CKE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PMU1_PCIE1_CTL BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PMU1_PCIE1_PDI BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PMU1_PCIE1_MSI BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PMU1_PCIE2_CTL BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PMU1_PCIE2_PDI BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PMU1_PCIE2_MSI BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PMU_ANALOG_USB0_P BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PMU_ANALOG_USB1_P BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PMU_ANALOG_PCIE0_P BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PMU_ANALOG_PCIE1_P BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PMU_ANALOG_PCIE2_P BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PMU_ANALOG_DSL_AFE BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PMU_ANALOG_DCDC_2V5 BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PMU_ANALOG_DCDC_1VX BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PMU_ANALOG_DCDC_1V0 BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define pmu_w32(x, y) ltq_w32((x), pmu_membase + (y))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define pmu_r32(x) ltq_r32(pmu_membase + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static void __iomem *pmu_membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) void __iomem *ltq_cgu_membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) void __iomem *ltq_ebu_membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static u32 ifccr = CGU_IFCCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static u32 pcicr = CGU_PCICR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static DEFINE_SPINLOCK(g_pmu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* legacy function kept alive to ease clkdev transition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) void ltq_pmu_enable(unsigned int module)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int retry = 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) spin_lock(&g_pmu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) pmu_w32(pmu_r32(PMU_PWDCR) & ~module, PMU_PWDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) do {} while (--retry && (pmu_r32(PMU_PWDSR) & module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) spin_unlock(&g_pmu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (!retry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) panic("activating PMU module failed!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) EXPORT_SYMBOL(ltq_pmu_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* legacy function kept alive to ease clkdev transition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) void ltq_pmu_disable(unsigned int module)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int retry = 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) spin_lock(&g_pmu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) pmu_w32(pmu_r32(PMU_PWDCR) | module, PMU_PWDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) do {} while (--retry && (!(pmu_r32(PMU_PWDSR) & module)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) spin_unlock(&g_pmu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (!retry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) pr_warn("deactivating PMU module failed!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) EXPORT_SYMBOL(ltq_pmu_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* enable a hw clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int cgu_enable(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* disable a hw clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static void cgu_disable(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* enable a clock gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int pmu_enable(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int retry = 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (of_machine_is_compatible("lantiq,ar10")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) || of_machine_is_compatible("lantiq,grx390")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) pmu_w32(clk->bits, PWDCR_EN_XRX(clk->module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) do {} while (--retry &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) (!(pmu_r32(PWDSR_XRX(clk->module)) & clk->bits)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) spin_lock(&g_pmu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) pmu_w32(pmu_r32(PWDCR(clk->module)) & ~clk->bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PWDCR(clk->module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) do {} while (--retry &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) (pmu_r32(PWDSR(clk->module)) & clk->bits));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) spin_unlock(&g_pmu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (!retry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) panic("activating PMU module failed!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* disable a clock gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static void pmu_disable(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int retry = 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (of_machine_is_compatible("lantiq,ar10")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) || of_machine_is_compatible("lantiq,grx390")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) pmu_w32(clk->bits, PWDCR_DIS_XRX(clk->module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) do {} while (--retry &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) (pmu_r32(PWDSR_XRX(clk->module)) & clk->bits));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) spin_lock(&g_pmu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) pmu_w32(pmu_r32(PWDCR(clk->module)) | clk->bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PWDCR(clk->module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) do {} while (--retry &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) (!(pmu_r32(PWDSR(clk->module)) & clk->bits)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) spin_unlock(&g_pmu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (!retry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) pr_warn("deactivating PMU module failed!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* the pci enable helper */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int pci_enable(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned int val = ltq_cgu_r32(ifccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* set bus clock speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (of_machine_is_compatible("lantiq,ar9") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) of_machine_is_compatible("lantiq,vr9")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) val &= ~0x1f00000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (clk->rate == CLOCK_33M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) val |= 0xe00000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) val |= 0x700000; /* 62.5M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) val &= ~0xf00000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (clk->rate == CLOCK_33M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) val |= 0x800000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) val |= 0x400000; /* 62.5M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ltq_cgu_w32(val, ifccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) pmu_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* enable the external clock as a source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int pci_ext_enable(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~(1 << 16), ifccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ltq_cgu_w32((1 << 30), pcicr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* disable the external clock as a source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static void pci_ext_disable(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ltq_cgu_w32(ltq_cgu_r32(ifccr) | (1 << 16), ifccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ltq_cgu_w32((1 << 31) | (1 << 30), pcicr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* enable a clockout source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int clkout_enable(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* get the correct rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (clk->rates[i] == clk->rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int shift = 14 - (2 * clk->module);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int enable = 7 - clk->module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned int val = ltq_cgu_r32(ifccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) val &= ~(3 << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) val |= i << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) val |= enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ltq_cgu_w32(val, ifccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* manage the clock gates via PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static void clkdev_add_pmu(const char *dev, const char *con, bool deactivate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) unsigned int module, unsigned int bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) clk->cl.dev_id = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) clk->cl.con_id = con;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) clk->cl.clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) clk->enable = pmu_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) clk->disable = pmu_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) clk->module = module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) clk->bits = bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (deactivate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * Disable it during the initialization. Module should enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * when used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) pmu_disable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) clkdev_add(&clk->cl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* manage the clock generator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static void clkdev_add_cgu(const char *dev, const char *con,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned int bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) clk->cl.dev_id = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) clk->cl.con_id = con;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) clk->cl.clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) clk->enable = cgu_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) clk->disable = cgu_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) clk->bits = bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) clkdev_add(&clk->cl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* pci needs its own enable function as the setup is a bit more complex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static unsigned long valid_pci_rates[] = {CLOCK_33M, CLOCK_62_5M, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static void clkdev_add_pci(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* main pci clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) clk->cl.dev_id = "17000000.pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) clk->cl.con_id = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) clk->cl.clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) clk->rate = CLOCK_33M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) clk->rates = valid_pci_rates;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) clk->enable = pci_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) clk->disable = pmu_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) clk->module = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) clk->bits = PMU_PCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) clkdev_add(&clk->cl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* use internal/external bus clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) clk_ext->cl.dev_id = "17000000.pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) clk_ext->cl.con_id = "external";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) clk_ext->cl.clk = clk_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) clk_ext->enable = pci_ext_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) clk_ext->disable = pci_ext_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) clkdev_add(&clk_ext->cl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* xway socs can generate clocks on gpio pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static unsigned long valid_clkout_rates[4][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {CLOCK_32_768K, CLOCK_1_536M, CLOCK_2_5M, CLOCK_12M, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {CLOCK_40M, CLOCK_12M, CLOCK_24M, CLOCK_48M, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {CLOCK_25M, CLOCK_40M, CLOCK_30M, CLOCK_60M, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {CLOCK_12M, CLOCK_50M, CLOCK_32_768K, CLOCK_25M, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static void clkdev_add_clkout(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) name = kzalloc(sizeof("clkout0"), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) sprintf(name, "clkout%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) clk->cl.dev_id = "1f103000.cgu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) clk->cl.con_id = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) clk->cl.clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) clk->rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) clk->rates = valid_clkout_rates[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) clk->enable = clkout_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) clk->module = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) clkdev_add(&clk->cl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* bring up all register ranges that we need for basic system control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) void __init ltq_soc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct resource res_pmu, res_cgu, res_ebu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct device_node *np_pmu =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) of_find_compatible_node(NULL, NULL, "lantiq,pmu-xway");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct device_node *np_cgu =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) of_find_compatible_node(NULL, NULL, "lantiq,cgu-xway");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct device_node *np_ebu =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) of_find_compatible_node(NULL, NULL, "lantiq,ebu-xway");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* check if all the core register ranges are available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (!np_pmu || !np_cgu || !np_ebu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) panic("Failed to load core nodes from devicetree");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (of_address_to_resource(np_pmu, 0, &res_pmu) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) of_address_to_resource(np_cgu, 0, &res_cgu) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) of_address_to_resource(np_ebu, 0, &res_ebu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) panic("Failed to get core resources");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (!request_mem_region(res_pmu.start, resource_size(&res_pmu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) res_pmu.name) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) !request_mem_region(res_cgu.start, resource_size(&res_cgu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) res_cgu.name) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) !request_mem_region(res_ebu.start, resource_size(&res_ebu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) res_ebu.name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) pr_err("Failed to request core resources");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) pmu_membase = ioremap(res_pmu.start, resource_size(&res_pmu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ltq_cgu_membase = ioremap(res_cgu.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) resource_size(&res_cgu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ltq_ebu_membase = ioremap(res_ebu.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) resource_size(&res_ebu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (!pmu_membase || !ltq_cgu_membase || !ltq_ebu_membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) panic("Failed to remap core resources");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* make sure to unprotect the memory region where flash is located */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* add our generic xway clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) clkdev_add_pmu("10000000.fpi", NULL, 0, 0, PMU_FPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) clkdev_add_pmu("1e100a00.gptu", NULL, 1, 0, PMU_GPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) clkdev_add_pmu("1e100bb0.stp", NULL, 1, 0, PMU_STP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) clkdev_add_pmu("1e104100.dma", NULL, 1, 0, PMU_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) clkdev_add_pmu("1e100800.spi", NULL, 1, 0, PMU_SPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) clkdev_add_pmu("1e105300.ebu", NULL, 0, 0, PMU_EBU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) clkdev_add_clkout();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* add the soc dependent clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (of_machine_is_compatible("lantiq,vr9")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ifccr = CGU_IFCCR_VR9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) pcicr = CGU_PCICR_VR9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) clkdev_add_pmu("1e180000.etop", NULL, 1, 0, PMU_PPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (!of_machine_is_compatible("lantiq,ase"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) clkdev_add_pci();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (of_machine_is_compatible("lantiq,grx390") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) of_machine_is_compatible("lantiq,ar10")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) clkdev_add_pmu("1e108000.switch", "gphy0", 0, 0, PMU_GPHY0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) clkdev_add_pmu("1e108000.switch", "gphy1", 0, 0, PMU_GPHY1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) clkdev_add_pmu("1e108000.switch", "gphy2", 0, 0, PMU_GPHY2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 2, PMU_ANALOG_USB0_P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 2, PMU_ANALOG_USB1_P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* rc 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) clkdev_add_pmu("1f106800.phy", "phy", 1, 2, PMU_ANALOG_PCIE0_P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) clkdev_add_pmu("1f106800.phy", "pdi", 1, 1, PMU1_PCIE_PDI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) clkdev_add_pmu("1d900000.pcie", "ctl", 1, 1, PMU1_PCIE_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* rc 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) clkdev_add_pmu("1f700400.phy", "phy", 1, 2, PMU_ANALOG_PCIE1_P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) clkdev_add_pmu("19000000.pcie", "msi", 1, 1, PMU1_PCIE1_MSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) clkdev_add_pmu("1f700400.phy", "pdi", 1, 1, PMU1_PCIE1_PDI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) clkdev_add_pmu("19000000.pcie", "ctl", 1, 1, PMU1_PCIE1_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (of_machine_is_compatible("lantiq,ase")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (ltq_cgu_r32(CGU_SYS) & (1 << 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) clkdev_add_static(CLOCK_266M, CLOCK_133M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) CLOCK_133M, CLOCK_266M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) clkdev_add_static(CLOCK_133M, CLOCK_133M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) CLOCK_133M, CLOCK_133M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) clkdev_add_pmu("1e180000.etop", "ppe", 1, 0, PMU_PPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) clkdev_add_pmu("1e180000.etop", "ephy", 1, 0, PMU_EPHY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_ASE_SDIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) } else if (of_machine_is_compatible("lantiq,grx390")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) clkdev_add_static(ltq_grx390_cpu_hz(), ltq_grx390_fpi_hz(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ltq_grx390_fpi_hz(), ltq_grx390_pp32_hz());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) clkdev_add_pmu("1e108000.switch", "gphy3", 0, 0, PMU_GPHY3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* rc 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) clkdev_add_pmu("1f106a00.pcie", "phy", 1, 2, PMU_ANALOG_PCIE2_P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) clkdev_add_pmu("1a800000.pcie", "msi", 1, 1, PMU1_PCIE2_MSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) clkdev_add_pmu("1f106a00.pcie", "pdi", 1, 1, PMU1_PCIE2_PDI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) clkdev_add_pmu("1a800000.pcie", "ctl", 1, 1, PMU1_PCIE2_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH | PMU_PPE_DP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) } else if (of_machine_is_compatible("lantiq,ar10")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) clkdev_add_static(ltq_ar10_cpu_hz(), ltq_ar10_fpi_hz(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ltq_ar10_fpi_hz(), ltq_ar10_pp32_hz());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) PMU_PPE_DP | PMU_PPE_TC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) clkdev_add_pmu("1e116000.mei", "afe", 1, 2, PMU_ANALOG_DSL_AFE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) } else if (of_machine_is_compatible("lantiq,vr9")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 0, PMU_USB1_P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1 | PMU_AHBM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) clkdev_add_pmu("1f106800.phy", "phy", 1, 1, PMU1_PCIE_PHY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) clkdev_add_pmu("1d900000.pcie", "bus", 1, 0, PMU_PCIE_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) clkdev_add_pmu("1f106800.phy", "pdi", 1, 1, PMU1_PCIE_PDI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) clkdev_add_pmu("1d900000.pcie", "ctl", 1, 1, PMU1_PCIE_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) clkdev_add_pmu(NULL, "ahb", 1, 0, PMU_AHBM | PMU_AHBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) clkdev_add_pmu("1e10b308.eth", NULL, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) PMU_PPE_QSB | PMU_PPE_TOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) clkdev_add_pmu("1e108000.switch", "gphy0", 0, 0, PMU_GPHY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) clkdev_add_pmu("1e108000.switch", "gphy1", 0, 0, PMU_GPHY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) } else if (of_machine_is_compatible("lantiq,ar9")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ltq_ar9_fpi_hz(), CLOCK_250M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 0, PMU_USB1_P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1 | PMU_AHBM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) clkdev_add_pmu("1e180000.etop", "switch", 1, 0, PMU_SWITCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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