^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012 John Crispin <john@phrozen.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Lantiq GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <lantiq_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "../clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* the magic ID byte of the core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define GPTU_MAGIC 0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* clock control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define GPTU_CLC 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* id register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define GPTU_ID 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* interrupt node enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define GPTU_IRNEN 0xf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* interrupt control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define GPTU_IRCR 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* interrupt capture register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GPTU_IRNCR 0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* there are 3 identical blocks of 2 timers. calculate register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GPTU_SHIFT(x) (x % 2 ? 4 : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GPTU_BASE(x) (((x >> 1) * 0x20) + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* timer control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define GPTU_CON(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* timer auto reload register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define GPTU_RUN(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* timer manual reload register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define GPTU_RLD(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* timer count register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define GPTU_CNT(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* GPTU_CON(x) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CON_CNT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CON_EDGE_ANY (BIT(7) | BIT(6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CON_SYNC BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CON_CLK_INT BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* GPTU_RUN(x) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RUN_SEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RUN_RL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* set clock to runmode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLC_RMC BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* bring core out of suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CLC_SUSPEND BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* the disable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CLC_DISABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define gptu_w32(x, y) ltq_w32((x), gptu_membase + (y))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define gptu_r32(x) ltq_r32(gptu_membase + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) enum gptu_timer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) TIMER1A = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) TIMER1B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) TIMER2A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) TIMER2B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) TIMER3A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) TIMER3B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static void __iomem *gptu_membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static struct resource irqres[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static irqreturn_t timer_irq_handler(int irq, void *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int timer = irq - irqres[0].start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) gptu_w32(1 << timer, GPTU_IRNCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static void gptu_hwinit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) gptu_w32(0x00, GPTU_IRNEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) gptu_w32(0xff, GPTU_IRNCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) gptu_w32(CLC_RMC | CLC_SUSPEND, GPTU_CLC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static void gptu_hwexit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) gptu_w32(0x00, GPTU_IRNEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) gptu_w32(0xff, GPTU_IRNCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) gptu_w32(CLC_DISABLE, GPTU_CLC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static int gptu_enable(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int ret = request_irq(irqres[clk->bits].start, timer_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) IRQF_TIMER, "gtpu", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) pr_err("gptu: failed to request irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) gptu_w32(CON_CNT | CON_EDGE_ANY | CON_SYNC | CON_CLK_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) GPTU_CON(clk->bits));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) gptu_w32(1, GPTU_RLD(clk->bits));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) gptu_w32(gptu_r32(GPTU_IRNEN) | BIT(clk->bits), GPTU_IRNEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) gptu_w32(RUN_SEN | RUN_RL, GPTU_RUN(clk->bits));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void gptu_disable(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) gptu_w32(0, GPTU_RUN(clk->bits));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) gptu_w32(0, GPTU_CON(clk->bits));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) gptu_w32(0, GPTU_RLD(clk->bits));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) gptu_w32(gptu_r32(GPTU_IRNEN) & ~BIT(clk->bits), GPTU_IRNEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) free_irq(irqres[clk->bits].start, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static inline void clkdev_add_gptu(struct device *dev, const char *con,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned int timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) clk->cl.dev_id = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) clk->cl.con_id = con;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) clk->cl.clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) clk->enable = gptu_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) clk->disable = gptu_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) clk->bits = timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) clkdev_add(&clk->cl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int gptu_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (of_irq_to_resource_table(pdev->dev.of_node, irqres, 6) != 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) dev_err(&pdev->dev, "Failed to get IRQ list\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* remap gptu register range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) gptu_membase = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (IS_ERR(gptu_membase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return PTR_ERR(gptu_membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* enable our clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) clk = clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) dev_err(&pdev->dev, "Failed to get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) clk_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* power up the core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) gptu_hwinit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* the gptu has a ID register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (((gptu_r32(GPTU_ID) >> 8) & 0xff) != GPTU_MAGIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) dev_err(&pdev->dev, "Failed to find magic\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) gptu_hwexit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) clk_disable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return -ENAVAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* register the clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) clkdev_add_gptu(&pdev->dev, "timer1a", TIMER1A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) clkdev_add_gptu(&pdev->dev, "timer1b", TIMER1B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) clkdev_add_gptu(&pdev->dev, "timer2a", TIMER2A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) clkdev_add_gptu(&pdev->dev, "timer2b", TIMER2B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) clkdev_add_gptu(&pdev->dev, "timer3a", TIMER3A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) clkdev_add_gptu(&pdev->dev, "timer3b", TIMER3B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) dev_info(&pdev->dev, "gptu: 6 timers loaded\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const struct of_device_id gptu_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { .compatible = "lantiq,gptu-xway" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static struct platform_driver dma_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .probe = gptu_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .name = "gptu-xway",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .of_match_table = gptu_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int __init gptu_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int ret = platform_driver_register(&dma_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) pr_info("gptu: Error registering platform driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) arch_initcall(gptu_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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