Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *   Copyright (C) 2011 John Crispin <john@phrozen.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <lantiq_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <xway_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define LTQ_DMA_ID		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define LTQ_DMA_CTRL		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define LTQ_DMA_CPOLL		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define LTQ_DMA_CS		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define LTQ_DMA_CCTRL		0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define LTQ_DMA_CDBA		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define LTQ_DMA_CDLEN		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define LTQ_DMA_CIS		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define LTQ_DMA_CIE		0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define LTQ_DMA_PS		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define LTQ_DMA_PCTRL		0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define LTQ_DMA_IRNEN		0xf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define DMA_ID_CHNR		GENMASK(26, 20)	/* channel number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define DMA_DESCPT		BIT(3)		/* descriptor complete irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define DMA_TX			BIT(8)		/* TX channel direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define DMA_CHAN_ON		BIT(0)		/* channel on / off bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define DMA_PDEN		BIT(6)		/* enable packet drop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define DMA_CHAN_RST		BIT(1)		/* channel on / off bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define DMA_RESET		BIT(0)		/* channel on / off bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define DMA_IRQ_ACK		0x7e		/* IRQ status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define DMA_POLL		BIT(31)		/* turn on channel polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define DMA_CLK_DIV4		BIT(6)		/* polling clock divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define DMA_PCTRL_2W_BURST	0x1		/* 2 word burst length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define DMA_PCTRL_4W_BURST	0x2		/* 4 word burst length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define DMA_PCTRL_8W_BURST	0x3		/* 8 word burst length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define DMA_TX_BURST_SHIFT	4		/* tx burst shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define DMA_RX_BURST_SHIFT	2		/* rx burst shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define DMA_ETOP_ENDIANNESS	(0xf << 8) /* endianness swap etop channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define DMA_WEIGHT	(BIT(17) | BIT(16))	/* default channel wheight */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define ltq_dma_r32(x)			ltq_r32(ltq_dma_membase + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define ltq_dma_w32(x, y)		ltq_w32(x, ltq_dma_membase + (y))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define ltq_dma_w32_mask(x, y, z)	ltq_w32_mask(x, y, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 						ltq_dma_membase + (z))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static void __iomem *ltq_dma_membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static DEFINE_SPINLOCK(ltq_dma_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) ltq_dma_enable_irq(struct ltq_dma_channel *ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	spin_lock_irqsave(&ltq_dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	ltq_dma_w32(ch->nr, LTQ_DMA_CS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	spin_unlock_irqrestore(&ltq_dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) EXPORT_SYMBOL_GPL(ltq_dma_enable_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) ltq_dma_disable_irq(struct ltq_dma_channel *ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	spin_lock_irqsave(&ltq_dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	ltq_dma_w32(ch->nr, LTQ_DMA_CS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	spin_unlock_irqrestore(&ltq_dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) EXPORT_SYMBOL_GPL(ltq_dma_disable_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) ltq_dma_ack_irq(struct ltq_dma_channel *ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	spin_lock_irqsave(&ltq_dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	ltq_dma_w32(ch->nr, LTQ_DMA_CS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	ltq_dma_w32(DMA_IRQ_ACK, LTQ_DMA_CIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	spin_unlock_irqrestore(&ltq_dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) EXPORT_SYMBOL_GPL(ltq_dma_ack_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) ltq_dma_open(struct ltq_dma_channel *ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	unsigned long flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	spin_lock_irqsave(&ltq_dma_lock, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	ltq_dma_w32(ch->nr, LTQ_DMA_CS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	ltq_dma_w32_mask(0, DMA_CHAN_ON, LTQ_DMA_CCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	spin_unlock_irqrestore(&ltq_dma_lock, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) EXPORT_SYMBOL_GPL(ltq_dma_open);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ltq_dma_close(struct ltq_dma_channel *ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	unsigned long flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	spin_lock_irqsave(&ltq_dma_lock, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	ltq_dma_w32(ch->nr, LTQ_DMA_CS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	spin_unlock_irqrestore(&ltq_dma_lock, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) EXPORT_SYMBOL_GPL(ltq_dma_close);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ltq_dma_alloc(struct ltq_dma_channel *ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	ch->desc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	ch->desc_base = dma_alloc_coherent(ch->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 					   LTQ_DESC_NUM * LTQ_DESC_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 					   &ch->phys, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	spin_lock_irqsave(&ltq_dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	ltq_dma_w32(ch->nr, LTQ_DMA_CS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	ltq_dma_w32(ch->phys, LTQ_DMA_CDBA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	ltq_dma_w32(LTQ_DESC_NUM, LTQ_DMA_CDLEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	ltq_dma_w32_mask(0, DMA_CHAN_RST, LTQ_DMA_CCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	while (ltq_dma_r32(LTQ_DMA_CCTRL) & DMA_CHAN_RST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	spin_unlock_irqrestore(&ltq_dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ltq_dma_alloc_tx(struct ltq_dma_channel *ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	ltq_dma_alloc(ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	spin_lock_irqsave(&ltq_dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	ltq_dma_w32(DMA_WEIGHT | DMA_TX, LTQ_DMA_CCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	spin_unlock_irqrestore(&ltq_dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) EXPORT_SYMBOL_GPL(ltq_dma_alloc_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ltq_dma_alloc_rx(struct ltq_dma_channel *ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	ltq_dma_alloc(ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	spin_lock_irqsave(&ltq_dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	ltq_dma_w32(DMA_WEIGHT, LTQ_DMA_CCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	spin_unlock_irqrestore(&ltq_dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) EXPORT_SYMBOL_GPL(ltq_dma_alloc_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ltq_dma_free(struct ltq_dma_channel *ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (!ch->desc_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	ltq_dma_close(ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	dma_free_coherent(ch->dev, LTQ_DESC_NUM * LTQ_DESC_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		ch->desc_base, ch->phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) EXPORT_SYMBOL_GPL(ltq_dma_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ltq_dma_init_port(int p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	ltq_dma_w32(p, LTQ_DMA_PS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	switch (p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	case DMA_PORT_ETOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		 * Tell the DMA engine to swap the endianness of data frames and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		 * drop packets if the channel arbitration fails.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		ltq_dma_w32_mask(0, DMA_ETOP_ENDIANNESS | DMA_PDEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			LTQ_DMA_PCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	case DMA_PORT_DEU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		ltq_dma_w32((DMA_PCTRL_2W_BURST << DMA_TX_BURST_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			(DMA_PCTRL_2W_BURST << DMA_RX_BURST_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			LTQ_DMA_PCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) EXPORT_SYMBOL_GPL(ltq_dma_init_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ltq_dma_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	unsigned int id, nchannels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	ltq_dma_membase = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if (IS_ERR(ltq_dma_membase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		panic("Failed to remap dma resource");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	/* power up and reset the dma engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	clk = clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		panic("Failed to get dma clock");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	clk_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	usleep_range(1, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	/* disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	ltq_dma_w32(0, LTQ_DMA_IRNEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	/* reset/configure each channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	id = ltq_dma_r32(LTQ_DMA_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	nchannels = ((id & DMA_ID_CHNR) >> 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	for (i = 0; i < nchannels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		ltq_dma_w32(i, LTQ_DMA_CS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		ltq_dma_w32(DMA_CHAN_RST, LTQ_DMA_CCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		"Init done - hw rev: %X, ports: %d, channels: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		id & 0x1f, (id >> 16) & 0xf, nchannels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const struct of_device_id dma_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	{ .compatible = "lantiq,dma-xway" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static struct platform_driver dma_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	.probe = ltq_dma_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		.name = "dma-xway",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		.of_match_table = dma_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) dma_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	return platform_driver_register(&dma_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) postcore_initcall(dma_init);