Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *  Copyright (C) 2010 John Crispin <john@phrozen.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <lantiq_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "../clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) static unsigned int ram_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define DDR_HZ ram_clocks[ltq_cgu_r32(CGU_SYS) & 0x3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /* legacy xway clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CGU_SYS			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /* vr9, ar10/grx390 clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CGU_SYS_XRX		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define CGU_IF_CLK_AR10		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) unsigned long ltq_danube_fpi_hz(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	unsigned long ddr_clock = DDR_HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	if (ltq_cgu_r32(CGU_SYS) & 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		return ddr_clock >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	return ddr_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) unsigned long ltq_danube_cpu_hz(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	switch (ltq_cgu_r32(CGU_SYS) & 0xc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		return CLOCK_333M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		return DDR_HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		return DDR_HZ << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		return DDR_HZ >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) unsigned long ltq_danube_pp32_hz(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 7) & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	unsigned long clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	switch (clksys) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		clk = CLOCK_240M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		clk = CLOCK_222M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		clk = CLOCK_133M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		clk = CLOCK_266M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) unsigned long ltq_ar9_sys_hz(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	if (((ltq_cgu_r32(CGU_SYS) >> 3) & 0x3) == 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		return CLOCK_393M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	return CLOCK_333M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) unsigned long ltq_ar9_fpi_hz(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	unsigned long sys = ltq_ar9_sys_hz();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	if (ltq_cgu_r32(CGU_SYS) & BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		return sys / 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		return sys / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) unsigned long ltq_ar9_cpu_hz(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	if (ltq_cgu_r32(CGU_SYS) & BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		return ltq_ar9_fpi_hz();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		return ltq_ar9_sys_hz();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned long ltq_vr9_cpu_hz(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	unsigned int cpu_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	unsigned long clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	cpu_sel = (ltq_cgu_r32(CGU_SYS_XRX) >> 4) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	switch (cpu_sel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		clk = CLOCK_600M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		clk = CLOCK_500M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		clk = CLOCK_393M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		clk = CLOCK_333M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		clk = CLOCK_196_608M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		clk = CLOCK_167M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	case 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		clk = CLOCK_125M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		clk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned long ltq_vr9_fpi_hz(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	unsigned int ocp_sel, cpu_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	unsigned long clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	cpu_clk = ltq_vr9_cpu_hz();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	ocp_sel = ltq_cgu_r32(CGU_SYS_XRX) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	switch (ocp_sel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		/* OCP ratio 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		clk = cpu_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		/* OCP ratio 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		clk = cpu_clk / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		/* OCP ratio 2.5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		clk = (cpu_clk * 2) / 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		/* OCP ratio 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		clk = cpu_clk / 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		clk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned long ltq_vr9_pp32_hz(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 16) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	unsigned long clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	switch (clksys) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		clk = CLOCK_500M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		clk = CLOCK_432M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		clk = CLOCK_288M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		clk = CLOCK_500M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned long ltq_ar10_cpu_hz(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	unsigned int clksys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	int cpu_fs = (ltq_cgu_r32(CGU_SYS_XRX) >> 8) & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	int freq_div = (ltq_cgu_r32(CGU_SYS_XRX) >> 4) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	switch (cpu_fs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		clksys = CLOCK_500M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		clksys = CLOCK_600M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		clksys = CLOCK_500M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	switch (freq_div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		return clksys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		return clksys >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		return clksys >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		return clksys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned long ltq_ar10_fpi_hz(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	int freq_fpi = (ltq_cgu_r32(CGU_IF_CLK_AR10) >> 25) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	switch (freq_fpi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		return CLOCK_300M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		return CLOCK_250M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		return CLOCK_150M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		return CLOCK_125M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		return CLOCK_125M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) unsigned long ltq_ar10_pp32_hz(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 16) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	unsigned long clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	switch (clksys) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		clk = CLOCK_250M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		clk = CLOCK_400M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		clk = CLOCK_250M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned long ltq_grx390_cpu_hz(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	unsigned int clksys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	int cpu_fs = ((ltq_cgu_r32(CGU_SYS_XRX) >> 9) & 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	int freq_div = ((ltq_cgu_r32(CGU_SYS_XRX) >> 4) & 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	switch (cpu_fs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		clksys = CLOCK_600M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		clksys = CLOCK_666M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		clksys = CLOCK_720M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		clksys = CLOCK_600M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	switch (freq_div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		return clksys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		return clksys >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		return clksys >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		return clksys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned long ltq_grx390_fpi_hz(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	/* fpi clock is derived from ddr_clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	unsigned int clksys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	int cpu_fs = ((ltq_cgu_r32(CGU_SYS_XRX) >> 9) & 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	int freq_div = ((ltq_cgu_r32(CGU_SYS_XRX)) & 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	switch (cpu_fs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		clksys = CLOCK_600M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		clksys = CLOCK_666M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		clksys = CLOCK_720M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		clksys = CLOCK_600M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	switch (freq_div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		return clksys >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		return clksys >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		return clksys >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned long ltq_grx390_pp32_hz(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 16) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	unsigned long clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	switch (clksys) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		clk = CLOCK_250M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		clk = CLOCK_432M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		clk = CLOCK_400M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		clk = CLOCK_250M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }