Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2011 John Crispin <john@phrozen.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <lantiq_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "../clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /* infrastructure control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define SYS1_INFRAC		0x00bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /* Configuration fuses for drivers and pll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define STATUS_CONFIG		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /* GPE frequency selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define GPPC_OFFSET		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define GPEFREQ_MASK		0x0000C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define GPEFREQ_OFFSET		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /* Clock status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define SYSCTL_CLKS		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /* Clock enable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SYSCTL_CLKEN		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /* Clock clear register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define SYSCTL_CLKCLR		0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /* Activation Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SYSCTL_ACTS		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* Activation Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SYSCTL_ACT		0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) /* Deactivation Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define SYSCTL_DEACT		0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /* reboot Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define SYSCTL_RBT		0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /* CPU0 Clock Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define SYS1_CPU0CC		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /* HRST_OUT_N Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define SYS1_HRSTOUTC		0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* clock divider bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define CPU0CC_CPUDIV		0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) /* Activation Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define ACTS_ASC0_ACT	0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define ACTS_SSC0	0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define ACTS_ASC1_ACT	0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define ACTS_I2C_ACT	0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define ACTS_P0		0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define ACTS_P1		0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define ACTS_P2		0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define ACTS_P3		0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define ACTS_P4		0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define ACTS_PADCTRL0	0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define ACTS_PADCTRL1	0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define ACTS_PADCTRL2	0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define ACTS_PADCTRL3	0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define ACTS_PADCTRL4	0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define sysctl_w32(m, x, y)	ltq_w32((x), sysctl_membase[m] + (y))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define sysctl_r32(m, x)	ltq_r32(sysctl_membase[m] + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define sysctl_w32_mask(m, clear, set, reg)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		sysctl_w32(m, (sysctl_r32(m, reg) & ~(clear)) | (set), reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define status_w32(x, y)	ltq_w32((x), status_membase + (y))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define status_r32(x)		ltq_r32(status_membase + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static void __iomem *sysctl_membase[3], *status_membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) void __iomem *ltq_sys1_membase, *ltq_ebu_membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) void falcon_trigger_hrst(int level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	sysctl_w32(SYSCTL_SYS1, level & 1, SYS1_HRSTOUTC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static inline void sysctl_wait(struct clk *clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		unsigned int test, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	int err = 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	do {} while (--err && ((sysctl_r32(clk->module, reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 					& clk->bits) != test));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		pr_err("module de/activation failed %d %08X %08X %08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			clk->module, clk->bits, test,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			sysctl_r32(clk->module, reg) & clk->bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static int sysctl_activate(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	sysctl_w32(clk->module, clk->bits, SYSCTL_ACT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	sysctl_wait(clk, clk->bits, SYSCTL_ACTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void sysctl_deactivate(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	sysctl_w32(clk->module, clk->bits, SYSCTL_CLKCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	sysctl_w32(clk->module, clk->bits, SYSCTL_DEACT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	sysctl_wait(clk, 0, SYSCTL_ACTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int sysctl_clken(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	sysctl_w32(clk->module, clk->bits, SYSCTL_ACT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	sysctl_wait(clk, clk->bits, SYSCTL_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static void sysctl_clkdis(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	sysctl_w32(clk->module, clk->bits, SYSCTL_CLKCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	sysctl_wait(clk, 0, SYSCTL_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static void sysctl_reboot(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	unsigned int act;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	unsigned int bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	act = sysctl_r32(clk->module, SYSCTL_ACT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	bits = ~act & clk->bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	if (bits != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		sysctl_w32(clk->module, bits, SYSCTL_CLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		sysctl_w32(clk->module, bits, SYSCTL_ACT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		sysctl_wait(clk, bits, SYSCTL_ACTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	sysctl_w32(clk->module, act & clk->bits, SYSCTL_RBT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	sysctl_wait(clk, clk->bits, SYSCTL_ACTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* enable the ONU core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static void falcon_gpe_enable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	unsigned int freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	/* if if the clock is already enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	status = sysctl_r32(SYSCTL_SYS1, SYS1_INFRAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (status & (1 << (GPPC_OFFSET + 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	freq = (status_r32(STATUS_CONFIG) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		GPEFREQ_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		GPEFREQ_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (freq == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		freq = 1; /* use 625MHz on unfused chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	/* apply new frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	sysctl_w32_mask(SYSCTL_SYS1, 7 << (GPPC_OFFSET + 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		freq << (GPPC_OFFSET + 2) , SYS1_INFRAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	/* enable new frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	sysctl_w32_mask(SYSCTL_SYS1, 0, 1 << (GPPC_OFFSET + 1), SYS1_INFRAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static inline void clkdev_add_sys(const char *dev, unsigned int module,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 					unsigned int bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	clk->cl.dev_id = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	clk->cl.con_id = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	clk->cl.clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	clk->module = module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	clk->bits = bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	clk->activate = sysctl_activate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	clk->deactivate = sysctl_deactivate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	clk->enable = sysctl_clken;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	clk->disable = sysctl_clkdis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	clk->reboot = sysctl_reboot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	clkdev_add(&clk->cl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) void __init ltq_soc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	struct device_node *np_status =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		of_find_compatible_node(NULL, NULL, "lantiq,status-falcon");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	struct device_node *np_ebu =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		of_find_compatible_node(NULL, NULL, "lantiq,ebu-falcon");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	struct device_node *np_sys1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		of_find_compatible_node(NULL, NULL, "lantiq,sys1-falcon");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	struct device_node *np_syseth =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		of_find_compatible_node(NULL, NULL, "lantiq,syseth-falcon");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	struct device_node *np_sysgpe =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		of_find_compatible_node(NULL, NULL, "lantiq,sysgpe-falcon");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct resource res_status, res_ebu, res_sys[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	/* check if all the core register ranges are available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (!np_status || !np_ebu || !np_sys1 || !np_syseth || !np_sysgpe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		panic("Failed to load core nodes from devicetree");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	if (of_address_to_resource(np_status, 0, &res_status) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			of_address_to_resource(np_ebu, 0, &res_ebu) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			of_address_to_resource(np_sys1, 0, &res_sys[0]) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			of_address_to_resource(np_syseth, 0, &res_sys[1]) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			of_address_to_resource(np_sysgpe, 0, &res_sys[2]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		panic("Failed to get core resources");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	if ((request_mem_region(res_status.start, resource_size(&res_status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 				res_status.name) < 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		(request_mem_region(res_ebu.start, resource_size(&res_ebu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 				res_ebu.name) < 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		(request_mem_region(res_sys[0].start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 				resource_size(&res_sys[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 				res_sys[0].name) < 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		(request_mem_region(res_sys[1].start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 				resource_size(&res_sys[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 				res_sys[1].name) < 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		(request_mem_region(res_sys[2].start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 				resource_size(&res_sys[2]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 				res_sys[2].name) < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		pr_err("Failed to request core resources");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	status_membase = ioremap(res_status.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 					resource_size(&res_status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	ltq_ebu_membase = ioremap(res_ebu.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 					resource_size(&res_ebu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (!status_membase || !ltq_ebu_membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		panic("Failed to remap core resources");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		sysctl_membase[i] = ioremap(res_sys[i].start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 						resource_size(&res_sys[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		if (!sysctl_membase[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			panic("Failed to remap sysctrl resources");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	ltq_sys1_membase = sysctl_membase[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	falcon_gpe_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	/* get our 3 static rates for cpu, fpi and io clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (ltq_sys1_r32(SYS1_CPU0CC) & CPU0CC_CPUDIV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	/* add our clock domains */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	clkdev_add_sys("1d810000.gpio", SYSCTL_SYSETH, ACTS_P0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	clkdev_add_sys("1d810100.gpio", SYSCTL_SYSETH, ACTS_P2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	clkdev_add_sys("1e800100.gpio", SYSCTL_SYS1, ACTS_P1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	clkdev_add_sys("1e800200.gpio", SYSCTL_SYS1, ACTS_P3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	clkdev_add_sys("1e800300.gpio", SYSCTL_SYS1, ACTS_P4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	clkdev_add_sys("1db01000.pad", SYSCTL_SYSETH, ACTS_PADCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	clkdev_add_sys("1db02000.pad", SYSCTL_SYSETH, ACTS_PADCTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	clkdev_add_sys("1e800400.pad", SYSCTL_SYS1, ACTS_PADCTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	clkdev_add_sys("1e800500.pad", SYSCTL_SYS1, ACTS_PADCTRL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	clkdev_add_sys("1e800600.pad", SYSCTL_SYS1, ACTS_PADCTRL4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	clkdev_add_sys("1e100b00.serial", SYSCTL_SYS1, ACTS_ASC1_ACT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	clkdev_add_sys("1e100c00.serial", SYSCTL_SYS1, ACTS_ASC0_ACT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	clkdev_add_sys("1e100d00.spi", SYSCTL_SYS1, ACTS_SSC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	clkdev_add_sys("1e200000.i2c", SYSCTL_SYS1, ACTS_I2C_ACT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }