Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2012 John Crispin <john@phrozen.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/traps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <lantiq_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "../prom.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SOC_FALCON	"Falcon"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SOC_FALCON_D	"Falcon-D"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SOC_FALCON_V	"Falcon-V"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SOC_FALCON_M	"Falcon-M"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define COMP_FALCON	"lantiq,falcon"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PART_SHIFT	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PART_MASK	0x0FFFF000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define REV_SHIFT	28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define REV_MASK	0xF0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SREV_SHIFT	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SREV_MASK	0x03C00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TYPE_SHIFT	26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TYPE_MASK	0x3C000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* reset, nmi and ejtag exception vectors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define BOOT_REG_BASE	(KSEG1 | 0x1F200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BOOT_RVEC	(BOOT_REG_BASE | 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BOOT_NVEC	(BOOT_REG_BASE | 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BOOT_EVEC	(BOOT_REG_BASE | 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) void __init ltq_soc_nmi_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	extern void (*nmi_handler)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	ltq_w32((unsigned long)&nmi_handler, (void *)BOOT_NVEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) void __init ltq_soc_ejtag_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	extern void (*ejtag_debug_handler)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	ltq_w32((unsigned long)&ejtag_debug_handler, (void *)BOOT_EVEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) void __init ltq_soc_detect(struct ltq_soc_info *i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	u32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	i->partnum = (ltq_r32(FALCON_CHIPID) & PART_MASK) >> PART_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	i->rev = (ltq_r32(FALCON_CHIPID) & REV_MASK) >> REV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	i->srev = ((ltq_r32(FALCON_CHIPCONF) & SREV_MASK) >> SREV_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	i->compatible = COMP_FALCON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	i->type = SOC_TYPE_FALCON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	sprintf(i->rev_type, "%c%d%d", (i->srev & 0x4) ? ('B') : ('A'),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		i->rev & 0x7, (i->srev & 0x3) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	switch (i->partnum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	case SOC_ID_FALCON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 		type = (ltq_r32(FALCON_CHIPTYPE) & TYPE_MASK) >> TYPE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 		case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 			i->name = SOC_FALCON_D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 		case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 			i->name = SOC_FALCON_V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 		case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 			i->name = SOC_FALCON_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 			i->name = SOC_FALCON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 		unreachable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 	board_nmi_handler_setup = ltq_soc_nmi_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 	board_ejtag_handler_setup = ltq_soc_ejtag_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }