^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * MIPS SIMD Architecture (MSA) context handling code for KVM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2015 Imagination Technologies Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/asmmacro.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/regdef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) .set noreorder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) .set noat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) LEAF(__kvm_save_msa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) st_d 0, VCPU_FPR0, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) st_d 1, VCPU_FPR1, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) st_d 2, VCPU_FPR2, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) st_d 3, VCPU_FPR3, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) st_d 4, VCPU_FPR4, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) st_d 5, VCPU_FPR5, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) st_d 6, VCPU_FPR6, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) st_d 7, VCPU_FPR7, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) st_d 8, VCPU_FPR8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) st_d 9, VCPU_FPR9, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) st_d 10, VCPU_FPR10, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) st_d 11, VCPU_FPR11, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) st_d 12, VCPU_FPR12, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) st_d 13, VCPU_FPR13, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) st_d 14, VCPU_FPR14, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) st_d 15, VCPU_FPR15, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) st_d 16, VCPU_FPR16, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) st_d 17, VCPU_FPR17, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) st_d 18, VCPU_FPR18, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) st_d 19, VCPU_FPR19, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) st_d 20, VCPU_FPR20, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) st_d 21, VCPU_FPR21, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) st_d 22, VCPU_FPR22, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) st_d 23, VCPU_FPR23, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) st_d 24, VCPU_FPR24, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) st_d 25, VCPU_FPR25, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) st_d 26, VCPU_FPR26, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) st_d 27, VCPU_FPR27, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) st_d 28, VCPU_FPR28, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) st_d 29, VCPU_FPR29, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) st_d 30, VCPU_FPR30, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) st_d 31, VCPU_FPR31, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) jr ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) END(__kvm_save_msa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) LEAF(__kvm_restore_msa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ld_d 0, VCPU_FPR0, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ld_d 1, VCPU_FPR1, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ld_d 2, VCPU_FPR2, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ld_d 3, VCPU_FPR3, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ld_d 4, VCPU_FPR4, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ld_d 5, VCPU_FPR5, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ld_d 6, VCPU_FPR6, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ld_d 7, VCPU_FPR7, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ld_d 8, VCPU_FPR8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ld_d 9, VCPU_FPR9, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ld_d 10, VCPU_FPR10, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ld_d 11, VCPU_FPR11, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ld_d 12, VCPU_FPR12, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ld_d 13, VCPU_FPR13, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ld_d 14, VCPU_FPR14, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ld_d 15, VCPU_FPR15, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ld_d 16, VCPU_FPR16, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ld_d 17, VCPU_FPR17, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ld_d 18, VCPU_FPR18, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ld_d 19, VCPU_FPR19, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ld_d 20, VCPU_FPR20, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ld_d 21, VCPU_FPR21, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ld_d 22, VCPU_FPR22, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ld_d 23, VCPU_FPR23, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ld_d 24, VCPU_FPR24, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ld_d 25, VCPU_FPR25, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ld_d 26, VCPU_FPR26, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ld_d 27, VCPU_FPR27, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ld_d 28, VCPU_FPR28, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ld_d 29, VCPU_FPR29, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ld_d 30, VCPU_FPR30, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ld_d 31, VCPU_FPR31, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) jr ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) END(__kvm_restore_msa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .macro kvm_restore_msa_upper wr, off, base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .set push
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .set noat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ld $1, \off(\base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) insert_d \wr, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #elif defined(CONFIG_CPU_LITTLE_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) lw $1, \off(\base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) insert_w \wr, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) lw $1, (\off+4)(\base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) insert_w \wr, 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #else /* CONFIG_CPU_BIG_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) lw $1, (\off+4)(\base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) insert_w \wr, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) lw $1, \off(\base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) insert_w \wr, 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .set pop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) LEAF(__kvm_restore_msa_upper)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) kvm_restore_msa_upper 0, VCPU_FPR0 +8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) kvm_restore_msa_upper 1, VCPU_FPR1 +8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) kvm_restore_msa_upper 2, VCPU_FPR2 +8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) kvm_restore_msa_upper 3, VCPU_FPR3 +8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) kvm_restore_msa_upper 4, VCPU_FPR4 +8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) kvm_restore_msa_upper 5, VCPU_FPR5 +8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) kvm_restore_msa_upper 6, VCPU_FPR6 +8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) kvm_restore_msa_upper 7, VCPU_FPR7 +8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) kvm_restore_msa_upper 8, VCPU_FPR8 +8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) kvm_restore_msa_upper 9, VCPU_FPR9 +8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) kvm_restore_msa_upper 10, VCPU_FPR10+8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) kvm_restore_msa_upper 11, VCPU_FPR11+8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) kvm_restore_msa_upper 12, VCPU_FPR12+8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) kvm_restore_msa_upper 13, VCPU_FPR13+8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) kvm_restore_msa_upper 14, VCPU_FPR14+8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) kvm_restore_msa_upper 15, VCPU_FPR15+8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) kvm_restore_msa_upper 16, VCPU_FPR16+8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) kvm_restore_msa_upper 17, VCPU_FPR17+8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) kvm_restore_msa_upper 18, VCPU_FPR18+8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) kvm_restore_msa_upper 19, VCPU_FPR19+8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) kvm_restore_msa_upper 20, VCPU_FPR20+8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) kvm_restore_msa_upper 21, VCPU_FPR21+8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) kvm_restore_msa_upper 22, VCPU_FPR22+8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) kvm_restore_msa_upper 23, VCPU_FPR23+8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) kvm_restore_msa_upper 24, VCPU_FPR24+8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) kvm_restore_msa_upper 25, VCPU_FPR25+8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) kvm_restore_msa_upper 26, VCPU_FPR26+8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) kvm_restore_msa_upper 27, VCPU_FPR27+8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) kvm_restore_msa_upper 28, VCPU_FPR28+8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) kvm_restore_msa_upper 29, VCPU_FPR29+8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) kvm_restore_msa_upper 30, VCPU_FPR30+8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) kvm_restore_msa_upper 31, VCPU_FPR31+8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) jr ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) END(__kvm_restore_msa_upper)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) LEAF(__kvm_restore_msacsr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) lw t0, VCPU_MSA_CSR(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * The ctcmsa must stay at this offset in __kvm_restore_msacsr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * See kvm_mips_csr_die_notify() which handles t0 containing a value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * which triggers an MSA FP Exception, which must be stepped over and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * ignored since the set cause bits must remain there for the guest.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) _ctcmsa MSA_CSR, t0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) jr ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) END(__kvm_restore_msacsr)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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