^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * KVM/MIPS: MIPS specific KVM APIs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Authors: Sanjay Lal <sanjayl@kymasys.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kdebug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/sched/signal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/fpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/pgalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/kvm_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "interrupt.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "commpage.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CREATE_TRACE_POINTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "trace.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #ifndef VECTORSPACING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define VECTORSPACING 0x100 /* for EI/VI mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct kvm_stats_debugfs_item debugfs_entries[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) VCPU_STAT("wait", wait_exits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) VCPU_STAT("cache", cache_exits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) VCPU_STAT("signal", signal_exits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) VCPU_STAT("interrupt", int_exits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) VCPU_STAT("cop_unusable", cop_unusable_exits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) VCPU_STAT("tlbmod", tlbmod_exits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) VCPU_STAT("tlbmiss_ld", tlbmiss_ld_exits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) VCPU_STAT("tlbmiss_st", tlbmiss_st_exits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) VCPU_STAT("addrerr_st", addrerr_st_exits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) VCPU_STAT("addrerr_ld", addrerr_ld_exits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) VCPU_STAT("syscall", syscall_exits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) VCPU_STAT("resvd_inst", resvd_inst_exits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) VCPU_STAT("break_inst", break_inst_exits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) VCPU_STAT("trap_inst", trap_inst_exits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) VCPU_STAT("msa_fpe", msa_fpe_exits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) VCPU_STAT("fpe", fpe_exits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) VCPU_STAT("msa_disabled", msa_disabled_exits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) VCPU_STAT("flush_dcache", flush_dcache_exits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #ifdef CONFIG_KVM_MIPS_VZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) VCPU_STAT("vz_gpsi", vz_gpsi_exits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) VCPU_STAT("vz_gsfc", vz_gsfc_exits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) VCPU_STAT("vz_hc", vz_hc_exits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) VCPU_STAT("vz_grr", vz_grr_exits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) VCPU_STAT("vz_gva", vz_gva_exits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) VCPU_STAT("vz_ghfc", vz_ghfc_exits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) VCPU_STAT("vz_gpa", vz_gpa_exits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) VCPU_STAT("vz_resvd", vz_resvd_exits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #ifdef CONFIG_CPU_LOONGSON64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) VCPU_STAT("vz_cpucfg", vz_cpucfg_exits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) VCPU_STAT("halt_successful_poll", halt_successful_poll),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) VCPU_STAT("halt_attempted_poll", halt_attempted_poll),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) VCPU_STAT("halt_poll_invalid", halt_poll_invalid),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) VCPU_STAT("halt_wakeup", halt_wakeup),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {NULL}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) bool kvm_trace_guest_mode_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int kvm_guest_mode_change_trace_reg(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) kvm_trace_guest_mode_change = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) void kvm_guest_mode_change_trace_unreg(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) kvm_trace_guest_mode_change = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * XXXKYMA: We are simulatoring a processor that has the WII bit set in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * Config7, so we are "runnable" if interrupts are pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return !!(vcpu->arch.pending_exceptions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int kvm_arch_hardware_enable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return kvm_mips_callbacks->hardware_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) void kvm_arch_hardware_disable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) kvm_mips_callbacks->hardware_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int kvm_arch_hardware_setup(void *opaque)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int kvm_arch_check_processor_compat(void *opaque)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) extern void kvm_init_loongson_ipi(struct kvm *kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) case KVM_VM_MIPS_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #ifdef CONFIG_KVM_MIPS_VZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) case KVM_VM_MIPS_VZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) case KVM_VM_MIPS_TE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Unsupported KVM type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Allocate page table to map GPA -> RPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) kvm->arch.gpa_mm.pgd = kvm_pgd_alloc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (!kvm->arch.gpa_mm.pgd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #ifdef CONFIG_CPU_LOONGSON64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) kvm_init_loongson_ipi(kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) void kvm_mips_free_vcpus(struct kvm *kvm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct kvm_vcpu *vcpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) kvm_for_each_vcpu(i, vcpu, kvm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) kvm_vcpu_destroy(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) mutex_lock(&kvm->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) kvm->vcpus[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) atomic_set(&kvm->online_vcpus, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) mutex_unlock(&kvm->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static void kvm_mips_free_gpa_pt(struct kvm *kvm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* It should always be safe to remove after flushing the whole range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) WARN_ON(!kvm_mips_flush_gpa_pt(kvm, 0, ~0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) pgd_free(NULL, kvm->arch.gpa_mm.pgd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) void kvm_arch_destroy_vm(struct kvm *kvm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) kvm_mips_free_vcpus(kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) kvm_mips_free_gpa_pt(kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) void kvm_arch_flush_shadow_all(struct kvm *kvm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Flush whole GPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) kvm_mips_flush_gpa_pt(kvm, 0, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Let implementation do the rest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) kvm_mips_callbacks->flush_shadow_all(kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct kvm_memory_slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * The slot has been made invalid (ready for moving or deletion), so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * need to ensure that it can no longer be accessed by any guest VCPUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) spin_lock(&kvm->mmu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Flush slot from GPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) kvm_mips_flush_gpa_pt(kvm, slot->base_gfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) slot->base_gfn + slot->npages - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Let implementation do the rest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) kvm_mips_callbacks->flush_shadow_memslot(kvm, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) spin_unlock(&kvm->mmu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int kvm_arch_prepare_memory_region(struct kvm *kvm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct kvm_memory_slot *memslot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) const struct kvm_userspace_memory_region *mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) enum kvm_mr_change change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) void kvm_arch_commit_memory_region(struct kvm *kvm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) const struct kvm_userspace_memory_region *mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct kvm_memory_slot *old,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) const struct kvm_memory_slot *new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) enum kvm_mr_change change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int needs_flush;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) __func__, kvm, mem->slot, mem->guest_phys_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) mem->memory_size, mem->userspace_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * If dirty page logging is enabled, write protect all pages in the slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * ready for dirty logging.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * There is no need to do this in any of the following cases:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * CREATE: No dirty mappings will already exist.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * MOVE/DELETE: The old mappings will already have been cleaned up by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * kvm_arch_flush_shadow_memslot()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (change == KVM_MR_FLAGS_ONLY &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) (!(old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) new->flags & KVM_MEM_LOG_DIRTY_PAGES)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) spin_lock(&kvm->mmu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* Write protect GPA page table entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) needs_flush = kvm_mips_mkclean_gpa_pt(kvm, new->base_gfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) new->base_gfn + new->npages - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Let implementation do the rest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (needs_flush)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) kvm_mips_callbacks->flush_shadow_memslot(kvm, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) spin_unlock(&kvm->mmu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static inline void dump_handler(const char *symbol, void *start, void *end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u32 *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) pr_debug("LEAF(%s)\n", symbol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pr_debug("\t.set push\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) pr_debug("\t.set noreorder\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) for (p = start; p < (u32 *)end; ++p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) pr_debug("\t.set\tpop\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) pr_debug("\tEND(%s)\n", symbol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* low level hrtimer wake routine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct kvm_vcpu *vcpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) kvm_mips_callbacks->queue_timer_int(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) vcpu->arch.wait = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) rcuwait_wake_up(&vcpu->wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return kvm_mips_count_timeout(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) int err, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) void *gebase, *p, *handler, *refill_start, *refill_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) kvm_debug("kvm @ %p: create cpu %d at %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) vcpu->kvm, vcpu->vcpu_id, vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) err = kvm_mips_callbacks->vcpu_init(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) HRTIMER_MODE_REL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * Allocate space for host mode exception handlers that handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * guest mode exits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (cpu_has_veic || cpu_has_vint)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) size = 0x200 + VECTORSPACING * 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) size = 0x4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (!gebase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) goto out_uninit_vcpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ALIGN(size, PAGE_SIZE), gebase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * Check new ebase actually fits in CP0_EBase. The lack of a write gate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * limits us to the low 512MB of physical address space. If the memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * we allocate is out of range, just give up now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) kvm_err("CP0_EBase.WG required for guest exception base %pK\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) gebase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) goto out_free_gebase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* Save new ebase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) vcpu->arch.guest_ebase = gebase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* Build guest exception vectors dynamically in unmapped memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) handler = gebase + 0x2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* TLB refill (or XTLB refill on 64-bit VZ where KX=1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) refill_start = gebase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (IS_ENABLED(CONFIG_KVM_MIPS_VZ) && IS_ENABLED(CONFIG_64BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) refill_start += 0x080;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) refill_end = kvm_mips_build_tlb_refill_exception(refill_start, handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* General Exception Entry point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) kvm_mips_build_exception(gebase + 0x180, handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* For vectored interrupts poke the exception code @ all offsets 0-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) kvm_debug("L1 Vectored handler @ %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) gebase + 0x200 + (i * VECTORSPACING));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* General exit handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) p = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) p = kvm_mips_build_exit(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* Guest entry routine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) vcpu->arch.vcpu_run = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) p = kvm_mips_build_vcpu_run(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* Dump the generated code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) pr_debug("#include <asm/asm.h>\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) pr_debug("#include <asm/regdef.h>\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) pr_debug("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dump_handler("kvm_tlb_refill", refill_start, refill_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* Invalidate the icache for these ranges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) flush_icache_range((unsigned long)gebase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * Allocate comm page for guest kernel, a TLB will be reserved for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * mapping GVA @ 0xFFFF8000 to this page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (!vcpu->arch.kseg0_commpage) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) goto out_free_gebase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) kvm_mips_commpage_init(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* Init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) vcpu->arch.last_sched_cpu = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) vcpu->arch.last_exec_cpu = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* Initial guest state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) err = kvm_mips_callbacks->vcpu_setup(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) goto out_free_commpage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) out_free_commpage:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) kfree(vcpu->arch.kseg0_commpage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) out_free_gebase:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) kfree(gebase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) out_uninit_vcpu:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) kvm_mips_callbacks->vcpu_uninit(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) hrtimer_cancel(&vcpu->arch.comparecount_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) kvm_mips_dump_stats(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) kvm_mmu_free_memory_caches(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) kfree(vcpu->arch.guest_ebase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) kfree(vcpu->arch.kseg0_commpage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) kvm_mips_callbacks->vcpu_uninit(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct kvm_guest_debug *dbg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int r = -EINTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) vcpu_load(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) kvm_sigset_activate(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (vcpu->mmio_needed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (!vcpu->mmio_is_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) kvm_mips_complete_mmio_load(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) vcpu->mmio_needed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (vcpu->run->immediate_exit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) lose_fpu(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) guest_enter_irqoff();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) trace_kvm_enter(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * Make sure the read of VCPU requests in vcpu_run() callback is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * reordered ahead of the write to vcpu->mode, or we could miss a TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * flush request while the requester sees the VCPU as outside of guest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * mode and not needing an IPI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) smp_store_mb(vcpu->mode, IN_GUEST_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) r = kvm_mips_callbacks->vcpu_run(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) trace_kvm_out(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) guest_exit_irqoff();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) local_irq_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) kvm_sigset_deactivate(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) vcpu_put(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct kvm_mips_interrupt *irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) int intr = (int)irq->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct kvm_vcpu *dvcpu = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (intr == kvm_priority_to_irq[MIPS_EXC_INT_IPI_1] ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) intr == kvm_priority_to_irq[MIPS_EXC_INT_IPI_2] ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) intr == (-kvm_priority_to_irq[MIPS_EXC_INT_IPI_1]) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) intr == (-kvm_priority_to_irq[MIPS_EXC_INT_IPI_2]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) (int)intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (irq->cpu == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) dvcpu = vcpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) dvcpu = vcpu->kvm->vcpus[irq->cpu];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (intr == 2 || intr == 3 || intr == 4 || intr == 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) kvm_mips_callbacks->queue_io_int(dvcpu, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) } else if (intr == -2 || intr == -3 || intr == -4 || intr == -6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) irq->cpu, irq->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) dvcpu->arch.wait = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) rcuwait_wake_up(&dvcpu->wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct kvm_mp_state *mp_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct kvm_mp_state *mp_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static u64 kvm_mips_get_one_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) KVM_REG_MIPS_R0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) KVM_REG_MIPS_R1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) KVM_REG_MIPS_R2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) KVM_REG_MIPS_R3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) KVM_REG_MIPS_R4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) KVM_REG_MIPS_R5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) KVM_REG_MIPS_R6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) KVM_REG_MIPS_R7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) KVM_REG_MIPS_R8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) KVM_REG_MIPS_R9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) KVM_REG_MIPS_R10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) KVM_REG_MIPS_R11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) KVM_REG_MIPS_R12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) KVM_REG_MIPS_R13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) KVM_REG_MIPS_R14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) KVM_REG_MIPS_R15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) KVM_REG_MIPS_R16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) KVM_REG_MIPS_R17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) KVM_REG_MIPS_R18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) KVM_REG_MIPS_R19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) KVM_REG_MIPS_R20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) KVM_REG_MIPS_R21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) KVM_REG_MIPS_R22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) KVM_REG_MIPS_R23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) KVM_REG_MIPS_R24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) KVM_REG_MIPS_R25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) KVM_REG_MIPS_R26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) KVM_REG_MIPS_R27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) KVM_REG_MIPS_R28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) KVM_REG_MIPS_R29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) KVM_REG_MIPS_R30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) KVM_REG_MIPS_R31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #ifndef CONFIG_CPU_MIPSR6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) KVM_REG_MIPS_HI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) KVM_REG_MIPS_LO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) KVM_REG_MIPS_PC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static u64 kvm_mips_get_one_regs_fpu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) KVM_REG_MIPS_FCR_IR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) KVM_REG_MIPS_FCR_CSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static u64 kvm_mips_get_one_regs_msa[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) KVM_REG_MIPS_MSA_IR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) KVM_REG_MIPS_MSA_CSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) unsigned long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ret = ARRAY_SIZE(kvm_mips_get_one_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* odd doubles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (boot_cpu_data.fpu_id & MIPS_FPIR_F64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) ret += 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (kvm_mips_guest_can_have_msa(&vcpu->arch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ret += kvm_mips_callbacks->num_regs(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) u64 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (copy_to_user(indices, kvm_mips_get_one_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) sizeof(kvm_mips_get_one_regs)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) indices += ARRAY_SIZE(kvm_mips_get_one_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (copy_to_user(indices, kvm_mips_get_one_regs_fpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) sizeof(kvm_mips_get_one_regs_fpu)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) for (i = 0; i < 32; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) index = KVM_REG_MIPS_FPR_32(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (copy_to_user(indices, &index, sizeof(index)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ++indices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* skip odd doubles if no F64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) index = KVM_REG_MIPS_FPR_64(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (copy_to_user(indices, &index, sizeof(index)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) ++indices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (kvm_mips_guest_can_have_msa(&vcpu->arch)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (copy_to_user(indices, kvm_mips_get_one_regs_msa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) sizeof(kvm_mips_get_one_regs_msa)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) for (i = 0; i < 32; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) index = KVM_REG_MIPS_VEC_128(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (copy_to_user(indices, &index, sizeof(index)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ++indices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return kvm_mips_callbacks->copy_reg_indices(vcpu, indices);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) const struct kvm_one_reg *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct mips_coproc *cop0 = vcpu->arch.cop0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) s64 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) s64 vs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) switch (reg->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* General purpose registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #ifndef CONFIG_CPU_MIPSR6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) case KVM_REG_MIPS_HI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) v = (long)vcpu->arch.hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) case KVM_REG_MIPS_LO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) v = (long)vcpu->arch.lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) case KVM_REG_MIPS_PC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) v = (long)vcpu->arch.pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* Floating point registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (!kvm_mips_guest_has_fpu(&vcpu->arch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) idx = reg->id - KVM_REG_MIPS_FPR_32(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* Odd singles in top of even double when FR=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (kvm_read_c0_guest_status(cop0) & ST0_FR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) v = get_fpr32(&fpu->fpr[idx], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (!kvm_mips_guest_has_fpu(&vcpu->arch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) idx = reg->id - KVM_REG_MIPS_FPR_64(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* Can't access odd doubles in FR=0 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) v = get_fpr64(&fpu->fpr[idx], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) case KVM_REG_MIPS_FCR_IR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (!kvm_mips_guest_has_fpu(&vcpu->arch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) v = boot_cpu_data.fpu_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) case KVM_REG_MIPS_FCR_CSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (!kvm_mips_guest_has_fpu(&vcpu->arch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) v = fpu->fcr31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* MIPS SIMD Architecture (MSA) registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (!kvm_mips_guest_has_msa(&vcpu->arch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* Can't access MSA registers in FR=0 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) idx = reg->id - KVM_REG_MIPS_VEC_128(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #ifdef CONFIG_CPU_LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /* least significant byte first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) vs[0] = get_fpr64(&fpu->fpr[idx], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) vs[1] = get_fpr64(&fpu->fpr[idx], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* most significant byte first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) vs[0] = get_fpr64(&fpu->fpr[idx], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) vs[1] = get_fpr64(&fpu->fpr[idx], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) case KVM_REG_MIPS_MSA_IR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (!kvm_mips_guest_has_msa(&vcpu->arch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) v = boot_cpu_data.msa_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) case KVM_REG_MIPS_MSA_CSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (!kvm_mips_guest_has_msa(&vcpu->arch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) v = fpu->msacsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* registers to be handled specially */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return put_user(v, uaddr64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) u32 v32 = (u32)v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return put_user(v32, uaddr32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) void __user *uaddr = (void __user *)(long)reg->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) const struct kvm_one_reg *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) struct mips_coproc *cop0 = vcpu->arch.cop0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) s64 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) s64 vs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (get_user(v, uaddr64) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) s32 v32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (get_user(v32, uaddr32) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) v = (s64)v32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) void __user *uaddr = (void __user *)(long)reg->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) switch (reg->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /* General purpose registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) case KVM_REG_MIPS_R0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /* Silently ignore requests to set $0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #ifndef CONFIG_CPU_MIPSR6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) case KVM_REG_MIPS_HI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) vcpu->arch.hi = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) case KVM_REG_MIPS_LO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) vcpu->arch.lo = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) case KVM_REG_MIPS_PC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) vcpu->arch.pc = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /* Floating point registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (!kvm_mips_guest_has_fpu(&vcpu->arch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) idx = reg->id - KVM_REG_MIPS_FPR_32(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /* Odd singles in top of even double when FR=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (kvm_read_c0_guest_status(cop0) & ST0_FR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) set_fpr32(&fpu->fpr[idx], 0, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (!kvm_mips_guest_has_fpu(&vcpu->arch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) idx = reg->id - KVM_REG_MIPS_FPR_64(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /* Can't access odd doubles in FR=0 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) set_fpr64(&fpu->fpr[idx], 0, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) case KVM_REG_MIPS_FCR_IR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (!kvm_mips_guest_has_fpu(&vcpu->arch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) /* Read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) case KVM_REG_MIPS_FCR_CSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (!kvm_mips_guest_has_fpu(&vcpu->arch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) fpu->fcr31 = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* MIPS SIMD Architecture (MSA) registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (!kvm_mips_guest_has_msa(&vcpu->arch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) idx = reg->id - KVM_REG_MIPS_VEC_128(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #ifdef CONFIG_CPU_LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /* least significant byte first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) set_fpr64(&fpu->fpr[idx], 0, vs[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) set_fpr64(&fpu->fpr[idx], 1, vs[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /* most significant byte first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) set_fpr64(&fpu->fpr[idx], 1, vs[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) set_fpr64(&fpu->fpr[idx], 0, vs[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) case KVM_REG_MIPS_MSA_IR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (!kvm_mips_guest_has_msa(&vcpu->arch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* Read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) case KVM_REG_MIPS_MSA_CSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (!kvm_mips_guest_has_msa(&vcpu->arch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) fpu->msacsr = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /* registers to be handled specially */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) struct kvm_enable_cap *cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) int r = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (cap->flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (cap->args[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) switch (cap->cap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) case KVM_CAP_MIPS_FPU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) vcpu->arch.fpu_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) case KVM_CAP_MIPS_MSA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) vcpu->arch.msa_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) r = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) long kvm_arch_vcpu_async_ioctl(struct file *filp, unsigned int ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) struct kvm_vcpu *vcpu = filp->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) void __user *argp = (void __user *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (ioctl == KVM_INTERRUPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) struct kvm_mips_interrupt irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (copy_from_user(&irq, argp, sizeof(irq)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) irq.irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) return kvm_vcpu_ioctl_interrupt(vcpu, &irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) return -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) struct kvm_vcpu *vcpu = filp->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) void __user *argp = (void __user *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) long r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) vcpu_load(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) switch (ioctl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) case KVM_SET_ONE_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) case KVM_GET_ONE_REG: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) struct kvm_one_reg reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) r = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (copy_from_user(®, argp, sizeof(reg)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (ioctl == KVM_SET_ONE_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) r = kvm_mips_set_reg(vcpu, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) r = kvm_mips_get_reg(vcpu, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) case KVM_GET_REG_LIST: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) struct kvm_reg_list __user *user_list = argp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) struct kvm_reg_list reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) unsigned n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) r = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (copy_from_user(®_list, user_list, sizeof(reg_list)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) n = reg_list.n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) reg_list.n = kvm_mips_num_regs(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (copy_to_user(user_list, ®_list, sizeof(reg_list)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) r = -E2BIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (n < reg_list.n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) r = kvm_mips_copy_reg_indices(vcpu, user_list->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) case KVM_ENABLE_CAP: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) struct kvm_enable_cap cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) r = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (copy_from_user(&cap, argp, sizeof(cap)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) r = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) vcpu_put(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) struct kvm_memory_slot *memslot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) /* Let implementation handle TLB/GVA invalidation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) kvm_mips_callbacks->flush_shadow_memslot(kvm, memslot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) long r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) switch (ioctl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) r = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) int kvm_arch_init(void *opaque)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (kvm_mips_callbacks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) kvm_err("kvm: module already exists\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) return -EEXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return kvm_mips_emulation_init(&kvm_mips_callbacks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) void kvm_arch_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) kvm_mips_callbacks = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) struct kvm_sregs *sregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) struct kvm_sregs *sregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) return -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) return -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) return -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) return VM_FAULT_SIGBUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) switch (ext) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) case KVM_CAP_ONE_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) case KVM_CAP_ENABLE_CAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) case KVM_CAP_READONLY_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) case KVM_CAP_SYNC_MMU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) case KVM_CAP_IMMEDIATE_EXIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) r = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) case KVM_CAP_NR_VCPUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) r = num_online_cpus();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) case KVM_CAP_MAX_VCPUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) r = KVM_MAX_VCPUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) case KVM_CAP_MAX_VCPU_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) r = KVM_MAX_VCPU_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) case KVM_CAP_MIPS_FPU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) /* We don't handle systems with inconsistent cpu_has_fpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) r = !!raw_cpu_has_fpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) case KVM_CAP_MIPS_MSA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) * We don't support MSA vector partitioning yet:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) * 1) It would require explicit support which can't be tested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) * yet due to lack of support in current hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) * 2) It extends the state that would need to be saved/restored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) * by e.g. QEMU for migration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) * When vector partitioning hardware becomes available, support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) * could be added by requiring a flag when enabling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) * KVM_CAP_MIPS_MSA capability to indicate that userland knows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) * to save/restore the appropriate extra state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) r = kvm_mips_callbacks->check_extension(kvm, ext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) return kvm_mips_pending_timer(vcpu) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) kvm_read_c0_guest_cause(vcpu->arch.cop0) & C_TI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) struct mips_coproc *cop0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (!vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) kvm_debug("VCPU Register Dump:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) for (i = 0; i < 32; i += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) vcpu->arch.gprs[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) vcpu->arch.gprs[i + 1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) cop0 = vcpu->arch.cop0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) kvm_debug("\tStatus: 0x%08x, Cause: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) kvm_read_c0_guest_status(cop0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) kvm_read_c0_guest_cause(cop0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) vcpu_load(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) vcpu->arch.gprs[i] = regs->gpr[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) vcpu->arch.hi = regs->hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) vcpu->arch.lo = regs->lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) vcpu->arch.pc = regs->pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) vcpu_put(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) vcpu_load(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) regs->gpr[i] = vcpu->arch.gprs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) regs->hi = vcpu->arch.hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) regs->lo = vcpu->arch.lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) regs->pc = vcpu->arch.pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) vcpu_put(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) struct kvm_translation *tr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) static void kvm_mips_set_c0_status(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) u32 status = read_c0_status();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (cpu_has_dsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) status |= (ST0_MX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) write_c0_status(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) ehb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) int kvm_mips_handle_exit(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) struct kvm_run *run = vcpu->run;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) u32 cause = vcpu->arch.host_cp0_cause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) u32 __user *opc = (u32 __user *) vcpu->arch.pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) enum emulation_result er = EMULATE_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) u32 inst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) int ret = RESUME_GUEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) vcpu->mode = OUTSIDE_GUEST_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) /* re-enable HTW before enabling interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) htw_start();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) /* Set a default exit reason */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) run->exit_reason = KVM_EXIT_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) run->ready_for_interrupt_injection = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) * Set the appropriate status bits based on host CPU features,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) * before we hit the scheduler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) kvm_mips_set_c0_status();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) local_irq_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) cause, opc, run, vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) trace_kvm_exit(vcpu, exccode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) * Do a privilege check, if in UM most of these exit conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) * end up causing an exception to be delivered to the Guest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) * Kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) er = kvm_mips_check_privilege(cause, opc, vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if (er == EMULATE_PRIV_FAIL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) goto skip_emul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) } else if (er == EMULATE_FAIL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) ret = RESUME_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) goto skip_emul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) switch (exccode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) case EXCCODE_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) ++vcpu->stat.int_exits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (need_resched())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) cond_resched();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) ret = RESUME_GUEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) case EXCCODE_CPU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) ++vcpu->stat.cop_unusable_exits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) /* XXXKYMA: Might need to return to user space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) ret = RESUME_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) case EXCCODE_MOD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) ++vcpu->stat.tlbmod_exits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) case EXCCODE_TLBS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) kvm_debug("TLB ST fault: cause %#x, status %#x, PC: %p, BadVaddr: %#lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) badvaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) ++vcpu->stat.tlbmiss_st_exits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) case EXCCODE_TLBL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) cause, opc, badvaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) ++vcpu->stat.tlbmiss_ld_exits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) case EXCCODE_ADES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) ++vcpu->stat.addrerr_st_exits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) case EXCCODE_ADEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) ++vcpu->stat.addrerr_ld_exits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) case EXCCODE_SYS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) ++vcpu->stat.syscall_exits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) ret = kvm_mips_callbacks->handle_syscall(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) case EXCCODE_RI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) ++vcpu->stat.resvd_inst_exits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) ret = kvm_mips_callbacks->handle_res_inst(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) case EXCCODE_BP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) ++vcpu->stat.break_inst_exits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) ret = kvm_mips_callbacks->handle_break(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) case EXCCODE_TR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) ++vcpu->stat.trap_inst_exits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) ret = kvm_mips_callbacks->handle_trap(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) case EXCCODE_MSAFPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) ++vcpu->stat.msa_fpe_exits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) case EXCCODE_FPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) ++vcpu->stat.fpe_exits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) ret = kvm_mips_callbacks->handle_fpe(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) case EXCCODE_MSADIS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) ++vcpu->stat.msa_disabled_exits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) case EXCCODE_GE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) /* defer exit accounting to handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) ret = kvm_mips_callbacks->handle_guest_exit(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if (cause & CAUSEF_BD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) opc += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) inst = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) kvm_get_badinstr(opc, vcpu, &inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) exccode, opc, inst, badvaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) kvm_read_c0_guest_status(vcpu->arch.cop0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) kvm_arch_vcpu_dump_regs(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) ret = RESUME_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) skip_emul:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) if (ret == RESUME_GUEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) kvm_vz_acquire_htimer(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) if (er == EMULATE_DONE && !(ret & RESUME_HOST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) kvm_mips_deliver_interrupts(vcpu, cause);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if (!(ret & RESUME_HOST)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) /* Only check for signals if not already exiting to userspace */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) if (signal_pending(current)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) run->exit_reason = KVM_EXIT_INTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) ret = (-EINTR << 2) | RESUME_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) ++vcpu->stat.signal_exits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) if (ret == RESUME_GUEST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) trace_kvm_reenter(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) * Make sure the read of VCPU requests in vcpu_reenter()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) * callback is not reordered ahead of the write to vcpu->mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) * or we could miss a TLB flush request while the requester sees
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) * the VCPU as outside of guest mode and not needing an IPI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) smp_store_mb(vcpu->mode, IN_GUEST_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) kvm_mips_callbacks->vcpu_reenter(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) * is live), restore FCR31 / MSACSR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) * This should be before returning to the guest exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) * vector, as it may well cause an [MSA] FP exception if there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) * are pending exception bits unmasked. (see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) * kvm_mips_csr_die_notifier() for how that is handled).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) read_c0_status() & ST0_CU1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) __kvm_restore_fcsr(&vcpu->arch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) if (kvm_mips_guest_has_msa(&vcpu->arch) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) read_c0_config5() & MIPS_CONF5_MSAEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) __kvm_restore_msacsr(&vcpu->arch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) /* Disable HTW before returning to guest or host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) htw_stop();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) /* Enable FPU for guest and restore context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) void kvm_own_fpu(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) struct mips_coproc *cop0 = vcpu->arch.cop0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) unsigned int sr, cfg5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) sr = kvm_read_c0_guest_status(cop0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) * If MSA state is already live, it is undefined how it interacts with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) * FR=0 FPU state, and we don't want to hit reserved instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) * exceptions trying to save the MSA state later when CU=1 && FR=1, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) * play it safe and save it first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) * get called when guest CU1 is set, however we can't trust the guest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) * not to clobber the status register directly via the commpage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) kvm_lose_fpu(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) * Enable FPU for guest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) * We set FR and FRE according to guest context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) change_c0_status(ST0_CU1 | ST0_FR, sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) if (cpu_has_fre) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) cfg5 = kvm_read_c0_guest_config5(cop0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) change_c0_config5(MIPS_CONF5_FRE, cfg5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) enable_fpu_hazard();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) /* If guest FPU state not active, restore it now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) __kvm_restore_fpu(&vcpu->arch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) #ifdef CONFIG_CPU_HAS_MSA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) /* Enable MSA for guest and restore context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) void kvm_own_msa(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) struct mips_coproc *cop0 = vcpu->arch.cop0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) unsigned int sr, cfg5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) * Enable FPU if enabled in guest, since we're restoring FPU context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) * anyway. We set FR and FRE according to guest context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) sr = kvm_read_c0_guest_status(cop0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) * If FR=0 FPU state is already live, it is undefined how it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) * interacts with MSA state, so play it safe and save it first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) if (!(sr & ST0_FR) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) kvm_lose_fpu(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) change_c0_status(ST0_CU1 | ST0_FR, sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) if (sr & ST0_CU1 && cpu_has_fre) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) cfg5 = kvm_read_c0_guest_config5(cop0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) change_c0_config5(MIPS_CONF5_FRE, cfg5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) /* Enable MSA for guest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) set_c0_config5(MIPS_CONF5_MSAEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) enable_fpu_hazard();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) case KVM_MIPS_AUX_FPU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) * Guest FPU state already loaded, only restore upper MSA state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) __kvm_restore_msa_upper(&vcpu->arch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) /* Neither FPU or MSA already active, restore full MSA state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) __kvm_restore_msa(&vcpu->arch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) if (kvm_mips_guest_has_fpu(&vcpu->arch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) KVM_TRACE_AUX_FPU_MSA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) /* Drop FPU & MSA without saving it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) void kvm_drop_fpu(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) disable_msa();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) clear_c0_status(ST0_CU1 | ST0_FR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) /* Save and disable FPU & MSA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) void kvm_lose_fpu(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) * With T&E, FPU & MSA get disabled in root context (hardware) when it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) * is disabled in guest context (software), but the register state in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) * the hardware may still be in use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) * This is why we explicitly re-enable the hardware before saving.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) set_c0_config5(MIPS_CONF5_MSAEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) enable_fpu_hazard();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) __kvm_save_msa(&vcpu->arch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) /* Disable MSA & FPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) disable_msa();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) clear_c0_status(ST0_CU1 | ST0_FR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) disable_fpu_hazard();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) set_c0_status(ST0_CU1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) enable_fpu_hazard();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) __kvm_save_fpu(&vcpu->arch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) /* Disable FPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) clear_c0_status(ST0_CU1 | ST0_FR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) disable_fpu_hazard();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) * exception if cause bits are set in the value being written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) static int kvm_mips_csr_die_notify(struct notifier_block *self,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) unsigned long cmd, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) struct die_args *args = (struct die_args *)ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) struct pt_regs *regs = args->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) unsigned long pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) /* Only interested in FPE and MSAFPE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) if (cmd != DIE_FP && cmd != DIE_MSAFP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) /* Return immediately if guest context isn't active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) if (!(current->flags & PF_VCPU))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) /* Should never get here from user mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) BUG_ON(user_mode(regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) pc = instruction_pointer(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) case DIE_FP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) /* match 2nd instruction in __kvm_restore_fcsr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) case DIE_MSAFP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) /* match 2nd/3rd instruction in __kvm_restore_msacsr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) if (!cpu_has_msa ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) pc > (unsigned long)&__kvm_restore_msacsr + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) /* Move PC forward a little and continue executing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) instruction_pointer(regs) += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) return NOTIFY_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) static struct notifier_block kvm_mips_csr_die_notifier = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .notifier_call = kvm_mips_csr_die_notify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) static u32 kvm_default_priority_to_irq[MIPS_EXC_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) [MIPS_EXC_INT_TIMER] = C_IRQ5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) [MIPS_EXC_INT_IO_1] = C_IRQ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) [MIPS_EXC_INT_IPI_1] = C_IRQ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) [MIPS_EXC_INT_IPI_2] = C_IRQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) static u32 kvm_loongson3_priority_to_irq[MIPS_EXC_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) [MIPS_EXC_INT_TIMER] = C_IRQ5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) [MIPS_EXC_INT_IO_1] = C_IRQ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) [MIPS_EXC_INT_IO_2] = C_IRQ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) [MIPS_EXC_INT_IPI_1] = C_IRQ4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) u32 *kvm_priority_to_irq = kvm_default_priority_to_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) u32 kvm_irq_to_priority(u32 irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) for (i = MIPS_EXC_INT_TIMER; i < MIPS_EXC_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) if (kvm_priority_to_irq[i] == (1 << (irq + 8)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) return MIPS_EXC_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) static int __init kvm_mips_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) if (cpu_has_mmid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) pr_warn("KVM does not yet support MMIDs. KVM Disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) ret = kvm_mips_entry_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) if (boot_cpu_type() == CPU_LOONGSON64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) kvm_priority_to_irq = kvm_loongson3_priority_to_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) register_die_notifier(&kvm_mips_csr_die_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) static void __exit kvm_mips_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) kvm_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) unregister_die_notifier(&kvm_mips_csr_die_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) module_init(kvm_mips_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) module_exit(kvm_mips_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) EXPORT_TRACEPOINT_SYMBOL(kvm_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags