Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * KVM/MIPS: Interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Authors: Sanjay Lal <sanjayl@kymasys.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * MIPS Exception Priorities, exceptions (including interrupts) are queued up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * for the guest in the order specified by their priorities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MIPS_EXC_RESET              0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MIPS_EXC_SRESET             1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MIPS_EXC_DEBUG_ST           2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MIPS_EXC_DEBUG              3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MIPS_EXC_DDB                4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MIPS_EXC_NMI                5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MIPS_EXC_MCHK               6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MIPS_EXC_INT_TIMER          7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MIPS_EXC_INT_IO_1           8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MIPS_EXC_INT_IO_2           9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MIPS_EXC_EXECUTE            10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MIPS_EXC_INT_IPI_1          11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MIPS_EXC_INT_IPI_2          12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MIPS_EXC_MAX                13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* XXXSL More to follow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define C_TI        (_ULCAST_(1) << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #ifdef CONFIG_KVM_MIPS_VZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define KVM_MIPS_IRQ_DELIVER_ALL_AT_ONCE (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define KVM_MIPS_IRQ_CLEAR_ALL_AT_ONCE   (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define KVM_MIPS_IRQ_DELIVER_ALL_AT_ONCE (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define KVM_MIPS_IRQ_CLEAR_ALL_AT_ONCE   (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) extern u32 *kvm_priority_to_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 kvm_irq_to_priority(u32 irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) void kvm_mips_queue_irq(struct kvm_vcpu *vcpu, unsigned int priority);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) void kvm_mips_dequeue_irq(struct kvm_vcpu *vcpu, unsigned int priority);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int kvm_mips_pending_timer(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) void kvm_mips_queue_timer_int_cb(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) void kvm_mips_dequeue_timer_int_cb(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) void kvm_mips_queue_io_int_cb(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 			      struct kvm_mips_interrupt *irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) void kvm_mips_dequeue_io_int_cb(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 				struct kvm_mips_interrupt *irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int kvm_mips_irq_deliver_cb(struct kvm_vcpu *vcpu, unsigned int priority,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 			    u32 cause);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int kvm_mips_irq_clear_cb(struct kvm_vcpu *vcpu, unsigned int priority,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 			  u32 cause);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) void kvm_mips_deliver_interrupts(struct kvm_vcpu *vcpu, u32 cause);