^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * MIPS SPRAM support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007, 2008 MIPS Technologies, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/fpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/r4kcache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/hazards.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * These definitions are correct for the 24K/34K/74K SPRAM sample
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * implementation. The 4KS interpreted the tags differently...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SPRAM_TAG0_ENABLE 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SPRAM_TAG0_PA_MASK 0xfffff000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SPRAM_TAG1_SIZE_MASK 0xfffff000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SPRAM_TAG_STRIDE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ERRCTL_SPRAM (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* errctl access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define read_c0_errctl(x) read_c0_ecc(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define write_c0_errctl(x) write_c0_ecc(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * Different semantics to the set_c0_* function built by __BUILD_SET_C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static unsigned int bis_c0_errctl(unsigned int set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) res = read_c0_errctl();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) write_c0_errctl(res | set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static void ispram_store_tag(unsigned int offset, unsigned int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned int errctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* enable SPRAM tag access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) errctl = bis_c0_errctl(ERRCTL_SPRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ehb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) write_c0_taglo(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ehb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) cache_op(Index_Store_Tag_I, CKSEG0|offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ehb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) write_c0_errctl(errctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ehb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static unsigned int ispram_load_tag(unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned int errctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* enable SPRAM tag access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) errctl = bis_c0_errctl(ERRCTL_SPRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ehb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) cache_op(Index_Load_Tag_I, CKSEG0 | offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ehb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) data = read_c0_taglo();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ehb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) write_c0_errctl(errctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ehb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static void dspram_store_tag(unsigned int offset, unsigned int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned int errctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* enable SPRAM tag access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) errctl = bis_c0_errctl(ERRCTL_SPRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ehb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) write_c0_dtaglo(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ehb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) cache_op(Index_Store_Tag_D, CKSEG0 | offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ehb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) write_c0_errctl(errctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ehb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static unsigned int dspram_load_tag(unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned int errctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) errctl = bis_c0_errctl(ERRCTL_SPRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ehb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) cache_op(Index_Load_Tag_D, CKSEG0 | offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ehb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) data = read_c0_dtaglo();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ehb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) write_c0_errctl(errctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ehb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void probe_spram(char *type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned int base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned int (*read)(unsigned int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) void (*write)(unsigned int, unsigned int))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned int firstsize = 0, lastsize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned int firstpa = 0, lastpa = 0, pa = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned int offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned int size, tag0, tag1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned int enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * The limit is arbitrary but avoids the loop running away if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * the SPRAM tags are implemented differently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) tag0 = read(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) tag1 = read(offset+SPRAM_TAG_STRIDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) pr_debug("DBG %s%d: tag0=%08x tag1=%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) type, i, tag0, tag1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) size = tag1 & SPRAM_TAG1_SIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (size == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (i != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* tags may repeat... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if ((pa == firstpa && size == firstsize) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) (pa == lastpa && size == lastsize))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Align base with size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) base = (base + size - 1) & ~(size-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* reprogram the base address base address and enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) tag0 = (base & SPRAM_TAG0_PA_MASK) | SPRAM_TAG0_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) write(offset, tag0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) base += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* reread the tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) tag0 = read(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) pa = tag0 & SPRAM_TAG0_PA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) enabled = tag0 & SPRAM_TAG0_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (i == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) firstpa = pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) firstsize = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) lastpa = pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) lastsize = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (strcmp(type, "DSPRAM") == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned int *vp = (unsigned int *)(CKSEG1 | pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned int v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define TDAT 0x5a5aa5a5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) vp[0] = TDAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) vp[1] = ~TDAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) v = vp[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (v != TDAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) printk(KERN_ERR "vp=%p wrote=%08x got=%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) vp, TDAT, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) v = vp[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (v != ~TDAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) printk(KERN_ERR "vp=%p wrote=%08x got=%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) vp+1, ~TDAT, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) pr_info("%s%d: PA=%08x,Size=%08x%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) type, i, pa, size, enabled ? ",enabled" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) offset += 2 * SPRAM_TAG_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) void spram_config(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned int config0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) switch (current_cpu_type()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) case CPU_24K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) case CPU_34K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) case CPU_74K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) case CPU_1004K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) case CPU_1074K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) case CPU_INTERAPTIV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) case CPU_PROAPTIV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) case CPU_P5600:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) case CPU_QEMU_GENERIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) case CPU_I6400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) case CPU_P6600:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) config0 = read_c0_config();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* FIXME: addresses are Malta specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (config0 & MIPS_CONF_ISP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) probe_spram("ISPRAM", 0x1c000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) &ispram_load_tag, &ispram_store_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (config0 & MIPS_CONF_DSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) probe_spram("DSPRAM", 0x1c100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) &dspram_load_tag, &dspram_store_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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