^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2004, 05, 06 MIPS Technologies, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Elizabeth Clarke (beth@mips.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Ralf Baechle (ralf@linux-mips.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/cpumask.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/sched/task_stack.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/hardirq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/mipsmtregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/mips_mt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/mips-cps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static void __init smvp_copy_vpe_config(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) write_vpe_c0_status(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) (read_c0_status() & ~(ST0_IM | ST0_IE | ST0_KSU)) | ST0_CU0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* set config to be the same as vpe0, particularly kseg0 coherency alg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) write_vpe_c0_config( read_c0_config());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* make sure there are no software interrupts pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) write_vpe_c0_cause(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Propagate Config7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) write_vpe_c0_config7(read_c0_config7());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) write_vpe_c0_count(read_c0_count());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static unsigned int __init smvp_vpe_init(unsigned int tc, unsigned int mvpconf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned int ncpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (tc > ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return ncpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Deactivate all but VPE 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (tc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned long tmp = read_vpe_c0_vpeconf0();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) tmp &= ~VPECONF0_VPA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* master VPE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) tmp |= VPECONF0_MVP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) write_vpe_c0_vpeconf0(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Record this as available CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) set_cpu_possible(tc, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) set_cpu_present(tc, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) __cpu_number_map[tc] = ++ncpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __cpu_logical_map[ncpu] = tc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Disable multi-threading with TC's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (tc != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) smvp_copy_vpe_config();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) cpu_set_vpe_id(&cpu_data[ncpu], tc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return ncpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static void __init smvp_tc_init(unsigned int tc, unsigned int mvpconf0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (!tc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* bind a TC to each VPE, May as well put all excess TC's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) on the last VPE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (tc >= (((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)+1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) write_tc_c0_tcbind(read_tc_c0_tcbind() | ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) write_tc_c0_tcbind(read_tc_c0_tcbind() | tc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* and set XTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | (tc << VPECONF0_XTC_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) tmp = read_tc_c0_tcstatus();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* mark not allocated and not dynamically allocatable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) tmp |= TCSTATUS_IXMT; /* interrupt exempt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) write_tc_c0_tcstatus(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) write_tc_c0_tchalt(TCHALT_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void vsmp_init_secondary(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* This is Malta specific: IPI,performance and timer interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (mips_gic_present())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) STATUSF_IP4 | STATUSF_IP5 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) STATUSF_IP6 | STATUSF_IP7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) STATUSF_IP6 | STATUSF_IP7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void vsmp_smp_finish(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* CDFIXME: remove this? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #ifdef CONFIG_MIPS_MT_FPAFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* If we have an FPU, enroll ourselves in the FPU-full mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (cpu_has_fpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #endif /* CONFIG_MIPS_MT_FPAFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) local_irq_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * Setup the PC, SP, and GP of a secondary processor and start it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * running!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * smp_bootstrap is the place to resume from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * __KSTK_TOS(idle) is apparently the stack pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * (unsigned long)idle->thread_info the gp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * assumes a 1:1 mapping of TC => VPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int vsmp_boot_secondary(int cpu, struct task_struct *idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct thread_info *gp = task_thread_info(idle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) dvpe();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) set_c0_mvpcontrol(MVPCONTROL_VPC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) settc(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* restart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) write_tc_c0_tcrestart((unsigned long)&smp_bootstrap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* enable the tc this vpe/cpu will be running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) write_tc_c0_tcstatus((read_tc_c0_tcstatus() & ~TCSTATUS_IXMT) | TCSTATUS_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) write_tc_c0_tchalt(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* enable the VPE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* stack pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) write_tc_gpr_sp( __KSTK_TOS(idle));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* global pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) write_tc_gpr_gp((unsigned long)gp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) flush_icache_range((unsigned long)gp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) (unsigned long)(gp + sizeof(struct thread_info)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* finally out of configuration and into chaos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) clear_c0_mvpcontrol(MVPCONTROL_VPC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) evpe(EVPE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * Common setup before any secondaries are started
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * Make sure all CPU's are in a sensible state before we boot any of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * secondaries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static void __init vsmp_smp_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned int mvpconf0, ntc, tc, ncpu = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned int nvpe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #ifdef CONFIG_MIPS_MT_FPAFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* If we have an FPU, enroll ourselves in the FPU-full mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (cpu_has_fpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) cpumask_set_cpu(0, &mt_fpu_cpumask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #endif /* CONFIG_MIPS_MT_FPAFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (!cpu_has_mipsmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* disable MT so we can configure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) dvpe();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) dmt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Put MVPE's into 'configuration state' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) set_c0_mvpcontrol(MVPCONTROL_VPC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) mvpconf0 = read_c0_mvpconf0();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ntc = (mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) smp_num_siblings = nvpe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* we'll always have more TC's than VPE's, so loop setting everything
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) to a sensible state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) for (tc = 0; tc <= ntc; tc++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) settc(tc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) smvp_tc_init(tc, mvpconf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ncpu = smvp_vpe_init(tc, mvpconf0, ncpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Release config state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) clear_c0_mvpcontrol(MVPCONTROL_VPC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* We'll wait until starting the secondaries before starting MVPE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) printk(KERN_INFO "Detected %i available secondary CPU(s)\n", ncpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static void __init vsmp_prepare_cpus(unsigned int max_cpus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) mips_mt_set_cpuoptions();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) const struct plat_smp_ops vsmp_smp_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .send_ipi_single = mips_smp_send_ipi_single,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .send_ipi_mask = mips_smp_send_ipi_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .init_secondary = vsmp_init_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .smp_finish = vsmp_smp_finish,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .boot_secondary = vsmp_boot_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .smp_setup = vsmp_smp_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .prepare_cpus = vsmp_prepare_cpus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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