Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2013 Imagination Technologies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Paul Burton <paul.burton@mips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/sched/task_stack.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/sched/hotplug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/bcache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/mips-cps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/mips_mt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/pm-cps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/r4kcache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/smp-cps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <asm/uasm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static bool threads_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static DECLARE_BITMAP(core_power, NR_CPUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) struct core_boot_config *mips_cps_core_bootcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static int __init setup_nothreads(char *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	threads_disabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) early_param("nothreads", setup_nothreads);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static unsigned core_vpe_count(unsigned int cluster, unsigned core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	if (threads_disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	return mips_cps_numvps(cluster, core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static void __init cps_smp_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	unsigned int nclusters, ncores, nvpes, core_vpes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	unsigned long core_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	int cl, c, v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	/* Detect & record VPE topology */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	nvpes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	nclusters = mips_cps_numclusters();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	pr_info("%s topology ", cpu_has_mips_r6 ? "VP" : "VPE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	for (cl = 0; cl < nclusters; cl++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		if (cl > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 			pr_cont(",");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		pr_cont("{");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		ncores = mips_cps_numcores(cl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		for (c = 0; c < ncores; c++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 			core_vpes = core_vpe_count(cl, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 			if (c > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 				pr_cont(",");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 			pr_cont("%u", core_vpes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 			/* Use the number of VPEs in cluster 0 core 0 for smp_num_siblings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 			if (!cl && !c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 				smp_num_siblings = core_vpes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 			for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 				cpu_set_cluster(&cpu_data[nvpes + v], cl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 				cpu_set_core(&cpu_data[nvpes + v], c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 				cpu_set_vpe_id(&cpu_data[nvpes + v], v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 			nvpes += core_vpes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		pr_cont("}");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	pr_cont(" total %u\n", nvpes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	/* Indicate present CPUs (CPU being synonymous with VPE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		set_cpu_possible(v, cpu_cluster(&cpu_data[v]) == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		set_cpu_present(v, cpu_cluster(&cpu_data[v]) == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		__cpu_number_map[v] = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		__cpu_logical_map[v] = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	/* Set a coherent default CCA (CWB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	change_c0_config(CONF_CM_CMASK, 0x5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	/* Core 0 is powered up (we're running on it) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	bitmap_set(core_power, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	/* Initialise core 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	mips_cps_core_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	/* Make core 0 coherent with everything */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	write_gcr_cl_coherence(0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	if (mips_cm_revision() >= CM_REV_CM3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		write_gcr_bev_base(core_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #ifdef CONFIG_MIPS_MT_FPAFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	/* If we have an FPU, enroll ourselves in the FPU-full mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	if (cpu_has_fpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		cpumask_set_cpu(0, &mt_fpu_cpumask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #endif /* CONFIG_MIPS_MT_FPAFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static void __init cps_prepare_cpus(unsigned int max_cpus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	unsigned ncores, core_vpes, c, cca;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	bool cca_unsuitable, cores_limited;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	u32 *entry_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	mips_mt_set_cpuoptions();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	/* Detect whether the CCA is unsuited to multi-core SMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	cca = read_c0_config() & CONF_CM_CMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	switch (cca) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	case 0x4: /* CWBE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	case 0x5: /* CWB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		/* The CCA is coherent, multi-core is fine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		cca_unsuitable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		/* CCA is not coherent, multi-core is not usable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		cca_unsuitable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	/* Warn the user if the CCA prevents multi-core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	cores_limited = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	if (cca_unsuitable || cpu_has_dc_aliases) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		for_each_present_cpu(c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			if (cpus_are_siblings(smp_processor_id(), c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			set_cpu_present(c, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			cores_limited = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if (cores_limited)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		pr_warn("Using only one core due to %s%s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			cca_unsuitable ? "unsuitable CCA" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 			(cca_unsuitable && cpu_has_dc_aliases) ? " & " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			cpu_has_dc_aliases ? "dcache aliasing" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	 * Patch the start of mips_cps_core_entry to provide:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	 * s0 = kseg0 CCA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	entry_code = (u32 *)&mips_cps_core_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	uasm_i_addiu(&entry_code, 16, 0, cca);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	blast_dcache_range((unsigned long)&mips_cps_core_entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			   (unsigned long)entry_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	bc_wback_inv((unsigned long)&mips_cps_core_entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		     (void *)entry_code - (void *)&mips_cps_core_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	__sync();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	/* Allocate core boot configuration structs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	ncores = mips_cps_numcores(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 					GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (!mips_cps_core_bootcfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		pr_err("Failed to allocate boot config for %u cores\n", ncores);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	/* Allocate VPE boot configuration structs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	for (c = 0; c < ncores; c++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		core_vpes = core_vpe_count(0, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		mips_cps_core_bootcfg[c].vpe_config = kcalloc(core_vpes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 				sizeof(*mips_cps_core_bootcfg[c].vpe_config),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 				GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		if (!mips_cps_core_bootcfg[c].vpe_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			pr_err("Failed to allocate %u VPE boot configs\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			       core_vpes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	/* Mark this CPU as booted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	atomic_set(&mips_cps_core_bootcfg[cpu_core(&current_cpu_data)].vpe_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		   1 << cpu_vpe_id(&current_cpu_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	/* Clean up allocations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (mips_cps_core_bootcfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		for (c = 0; c < ncores; c++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 			kfree(mips_cps_core_bootcfg[c].vpe_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		kfree(mips_cps_core_bootcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		mips_cps_core_bootcfg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	/* Effectively disable SMP by declaring CPUs not present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	for_each_possible_cpu(c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		if (c == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		set_cpu_present(c, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static void boot_core(unsigned int core, unsigned int vpe_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	u32 stat, seq_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	unsigned timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	/* Select the appropriate core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	/* Set its reset vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	/* Ensure its coherency is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	write_gcr_co_coherence(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	/* Start it with the legacy memory map and exception base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	write_gcr_co_reset_ext_base(CM_GCR_Cx_RESET_EXT_BASE_UEB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	/* Ensure the core can access the GCRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	set_gcr_access(1 << core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if (mips_cpc_present()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		/* Reset the core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		mips_cpc_lock_other(core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		if (mips_cm_revision() >= CM_REV_CM3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			/* Run only the requested VP following the reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			write_cpc_co_vp_stop(0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			write_cpc_co_vp_run(1 << vpe_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 			 * Ensure that the VP_RUN register is written before the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			 * core leaves reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		write_cpc_co_cmd(CPC_Cx_CMD_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		timeout = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		while (true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			stat = read_cpc_co_stat_conf();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 			seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			/* U6 == coherent execution, ie. the core is up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 			/* Delay a little while before we start warning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			if (timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 				timeout--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 				mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 			pr_warn("Waiting for core %u to start... STAT_CONF=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 				core, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			mdelay(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		mips_cpc_unlock_other();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		/* Take the core out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		write_gcr_co_reset_release(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	mips_cm_unlock_other();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	/* The core is now powered up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	bitmap_set(core_power, core, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static void remote_vpe_boot(void *dummy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	unsigned core = cpu_core(&current_cpu_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	mips_cps_boot_vpes(core_cfg, cpu_vpe_id(&current_cpu_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int cps_boot_secondary(int cpu, struct task_struct *idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	unsigned core = cpu_core(&cpu_data[cpu]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	unsigned long core_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	unsigned int remote;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	/* We don't yet support booting CPUs in other clusters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	if (cpu_cluster(&cpu_data[cpu]) != cpu_cluster(&raw_current_cpu_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	vpe_cfg->pc = (unsigned long)&smp_bootstrap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	vpe_cfg->sp = __KSTK_TOS(idle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	vpe_cfg->gp = (unsigned long)task_thread_info(idle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	if (!test_bit(core, core_power)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		/* Boot a VPE on a powered down core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		boot_core(core, vpe_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	if (cpu_has_vp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		write_gcr_co_reset_base(core_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		mips_cm_unlock_other();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	if (!cpus_are_siblings(cpu, smp_processor_id())) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		/* Boot a VPE on another powered up core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		for (remote = 0; remote < NR_CPUS; remote++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 			if (!cpus_are_siblings(cpu, remote))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 			if (cpu_online(remote))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		if (remote >= NR_CPUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			pr_crit("No online CPU in core %u to start CPU%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 				core, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		err = smp_call_function_single(remote, remote_vpe_boot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 					       NULL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 			panic("Failed to call remote CPU\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	BUG_ON(!cpu_has_mipsmt && !cpu_has_vp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	/* Boot a VPE on this core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	mips_cps_boot_vpes(core_cfg, vpe_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static void cps_init_secondary(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	/* Disable MT - we only want to run 1 TC per VPE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	if (cpu_has_mipsmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		dmt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	if (mips_cm_revision() >= CM_REV_CM3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		unsigned int ident = read_gic_vl_ident();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		 * Ensure that our calculation of the VP ID matches up with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		 * what the GIC reports, otherwise we'll have configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		 * interrupts incorrectly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		BUG_ON(ident != mips_cm_vp_id(smp_processor_id()));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	if (cpu_has_veic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		clear_c0_status(ST0_IM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 					 STATUSF_IP4 | STATUSF_IP5 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 					 STATUSF_IP6 | STATUSF_IP7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static void cps_smp_finish(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #ifdef CONFIG_MIPS_MT_FPAFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	/* If we have an FPU, enroll ourselves in the FPU-full mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	if (cpu_has_fpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #endif /* CONFIG_MIPS_MT_FPAFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	local_irq_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_KEXEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) enum cpu_death {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	CPU_DEATH_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	CPU_DEATH_POWER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static void cps_shutdown_this_cpu(enum cpu_death death)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	unsigned int cpu, core, vpe_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	core = cpu_core(&cpu_data[cpu]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	if (death == CPU_DEATH_HALT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		vpe_id = cpu_vpe_id(&cpu_data[cpu]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		pr_debug("Halting core %d VP%d\n", core, vpe_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		if (cpu_has_mipsmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 			/* Halt this TC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 			write_c0_tchalt(TCHALT_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 			instruction_hazard();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		} else if (cpu_has_vp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 			write_cpc_cl_vp_stop(1 << vpe_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 			/* Ensure that the VP_STOP register is written */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 			wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		pr_debug("Gating power to core %d\n", core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		/* Power down the core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		cps_pm_enter_state(CPS_PM_POWER_GATED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #ifdef CONFIG_KEXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static void cps_kexec_nonboot_cpu(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	if (cpu_has_mipsmt || cpu_has_vp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 		cps_shutdown_this_cpu(CPU_DEATH_HALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 		cps_shutdown_this_cpu(CPU_DEATH_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #endif /* CONFIG_KEXEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #endif /* CONFIG_HOTPLUG_CPU || CONFIG_KEXEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static int cps_cpu_disable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	unsigned cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	struct core_boot_config *core_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	if (!cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	if (!cps_pm_support_state(CPS_PM_POWER_GATED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	core_cfg = &mips_cps_core_bootcfg[cpu_core(&current_cpu_data)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	atomic_sub(1 << cpu_vpe_id(&current_cpu_data), &core_cfg->vpe_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	smp_mb__after_atomic();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	set_cpu_online(cpu, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	calculate_cpu_foreign_map();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static unsigned cpu_death_sibling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static enum cpu_death cpu_death;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) void play_dead(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	unsigned int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	idle_task_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	cpu_death = CPU_DEATH_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	pr_debug("CPU%d going offline\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	if (cpu_has_mipsmt || cpu_has_vp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 		/* Look for another online VPE within the core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 		for_each_online_cpu(cpu_death_sibling) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 			if (!cpus_are_siblings(cpu, cpu_death_sibling))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 			 * There is an online VPE within the core. Just halt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 			 * this TC and leave the core alone.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 			cpu_death = CPU_DEATH_HALT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	/* This CPU has chosen its way out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	(void)cpu_report_death();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	cps_shutdown_this_cpu(cpu_death);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	/* This should never be reached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	panic("Failed to offline CPU %u", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static void wait_for_sibling_halt(void *ptr_cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	unsigned cpu = (unsigned long)ptr_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	unsigned halted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 		local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 		settc(vpe_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 		halted = read_tc_c0_tchalt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 		local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	} while (!(halted & TCHALT_H));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static void cps_cpu_die(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	unsigned core = cpu_core(&cpu_data[cpu]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	unsigned int vpe_id = cpu_vpe_id(&cpu_data[cpu]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	ktime_t fail_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	unsigned stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	/* Wait for the cpu to choose its way out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	if (!cpu_wait_death(cpu, 5)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 		pr_err("CPU%u: didn't offline\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	 * Now wait for the CPU to actually offline. Without doing this that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	 * offlining may race with one or more of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	 *   - Onlining the CPU again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 	 *   - Powering down the core if another VPE within it is offlined.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	 *   - A sibling VPE entering a non-coherent state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	 * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 	 * with which we could race, so do nothing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	if (cpu_death == CPU_DEATH_POWER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 		 * Wait for the core to enter a powered down or clock gated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 		 * state, the latter happening when a JTAG probe is connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 		 * in which case the CPC will refuse to power down the core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 		fail_time = ktime_add_ms(ktime_get(), 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 		do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 			mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 			mips_cpc_lock_other(core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 			stat = read_cpc_co_stat_conf();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 			stat &= CPC_Cx_STAT_CONF_SEQSTATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 			stat >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 			mips_cpc_unlock_other();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 			mips_cm_unlock_other();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 			if (stat == CPC_Cx_STAT_CONF_SEQSTATE_D0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 			    stat == CPC_Cx_STAT_CONF_SEQSTATE_D2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 			    stat == CPC_Cx_STAT_CONF_SEQSTATE_U2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 			 * The core ought to have powered down, but didn't &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 			 * now we don't really know what state it's in. It's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 			 * likely that its _pwr_up pin has been wired to logic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 			 * 1 & it powered back up as soon as we powered it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 			 * down...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 			 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 			 * The best we can do is warn the user & continue in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 			 * the hope that the core is doing nothing harmful &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 			 * might behave properly if we online it later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 			if (WARN(ktime_after(ktime_get(), fail_time),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 				 "CPU%u hasn't powered down, seq. state %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 				 cpu, stat))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 		} while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 		/* Indicate the core is powered off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 		bitmap_clear(core_power, core, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 	} else if (cpu_has_mipsmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 		 * Have a CPU with access to the offlined CPUs registers wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 		 * for its TC to halt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 		err = smp_call_function_single(cpu_death_sibling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 					       wait_for_sibling_halt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 					       (void *)(unsigned long)cpu, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 		if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 			panic("Failed to call remote sibling CPU\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 	} else if (cpu_has_vp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 		do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 			mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 			stat = read_cpc_co_vp_running();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 			mips_cm_unlock_other();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 		} while (stat & (1 << vpe_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #endif /* CONFIG_HOTPLUG_CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static const struct plat_smp_ops cps_smp_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 	.smp_setup		= cps_smp_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 	.prepare_cpus		= cps_prepare_cpus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 	.boot_secondary		= cps_boot_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 	.init_secondary		= cps_init_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 	.smp_finish		= cps_smp_finish,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 	.send_ipi_single	= mips_smp_send_ipi_single,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 	.send_ipi_mask		= mips_smp_send_ipi_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 	.cpu_disable		= cps_cpu_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 	.cpu_die		= cps_cpu_die,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #ifdef CONFIG_KEXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 	.kexec_nonboot_cpu	= cps_kexec_nonboot_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) bool mips_cps_smp_in_use(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 	extern const struct plat_smp_ops *mp_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 	return mp_ops == &cps_smp_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) int register_cps_smp_ops(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 	if (!mips_cm_present()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 		pr_warn("MIPS CPS SMP unable to proceed without a CM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 	/* check we have a GIC - we need one for IPIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 	if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 		pr_warn("MIPS CPS SMP unable to proceed without a GIC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 	register_smp_ops(&cps_smp_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }