Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 1996, 98, 99, 2000, 01 Ralf Baechle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Multi-arch abstraction and asm macros for easier reading:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Carsten Langgaard, carstenl@mips.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * Copyright (C) 2000 MIPS Technologies, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * Copyright (C) 1999, 2001 Silicon Graphics, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/asmmacro.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/fpregdef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/regdef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #undef fp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	.macro	EX insn, reg, src
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	.set	push
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	SET_HARDFLOAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	.set	nomacro
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) .ex\@:	\insn	\reg, \src
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	.set	pop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	.section __ex_table,"a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	PTR	.ex\@, fault
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	.previous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * Save a thread's fp context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) LEAF(_save_fp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) EXPORT_SYMBOL(_save_fp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)     defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	mfc0	t0, CP0_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	fpu_save_double a0 t0 t1		# clobbers t1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	jr	ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	END(_save_fp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * Restore a thread's fp context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) LEAF(_restore_fp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)     defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	mfc0	t0, CP0_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	fpu_restore_double a0 t0 t1		# clobbers t1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	jr	ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	END(_restore_fp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #ifdef CONFIG_CPU_HAS_MSA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  * Save a thread's MSA vector context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) LEAF(_save_msa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) EXPORT_SYMBOL(_save_msa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	msa_save_all	a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	jr	ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	END(_save_msa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  * Restore a thread's MSA vector context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) LEAF(_restore_msa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	msa_restore_all	a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	jr	ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	END(_restore_msa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) LEAF(_init_msa_upper)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	msa_init_all_upper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	jr	ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	END(_init_msa_upper)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	.set	noreorder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)  * _save_fp_context() - save FP context from the FPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  * @a0 - pointer to fpregs field of sigcontext
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  * @a1 - pointer to fpc_csr field of sigcontext
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)  * Save FP context, including the 32 FP data registers and the FP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  * control & status register, from the FPU to signal context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) LEAF(_save_fp_context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	.set	push
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	SET_HARDFLOAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	cfc1	t1, fcr31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	.set	pop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)     defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	.set	push
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	SET_HARDFLOAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	.set	mips32r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	.set	fp=64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	mfc0	t0, CP0_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	sll	t0, t0, 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	bgez	t0, 1f			# skip storing odd if FR=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	/* Store the 16 odd double precision registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	EX	sdc1 $f1, 8(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	EX	sdc1 $f3, 24(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	EX	sdc1 $f5, 40(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	EX	sdc1 $f7, 56(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	EX	sdc1 $f9, 72(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	EX	sdc1 $f11, 88(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	EX	sdc1 $f13, 104(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	EX	sdc1 $f15, 120(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	EX	sdc1 $f17, 136(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	EX	sdc1 $f19, 152(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	EX	sdc1 $f21, 168(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	EX	sdc1 $f23, 184(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	EX	sdc1 $f25, 200(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	EX	sdc1 $f27, 216(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	EX	sdc1 $f29, 232(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	EX	sdc1 $f31, 248(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 1:	.set	pop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	.set push
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	SET_HARDFLOAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	/* Store the 16 even double precision registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	EX	sdc1 $f0, 0(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	EX	sdc1 $f2, 16(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	EX	sdc1 $f4, 32(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	EX	sdc1 $f6, 48(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	EX	sdc1 $f8, 64(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	EX	sdc1 $f10, 80(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	EX	sdc1 $f12, 96(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	EX	sdc1 $f14, 112(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	EX	sdc1 $f16, 128(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	EX	sdc1 $f18, 144(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	EX	sdc1 $f20, 160(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	EX	sdc1 $f22, 176(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	EX	sdc1 $f24, 192(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	EX	sdc1 $f26, 208(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	EX	sdc1 $f28, 224(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	EX	sdc1 $f30, 240(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	EX	sw t1, 0(a1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	jr	ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	 li	v0, 0					# success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.set pop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	END(_save_fp_context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  * _restore_fp_context() - restore FP context to the FPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  * @a0 - pointer to fpregs field of sigcontext
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  * @a1 - pointer to fpc_csr field of sigcontext
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)  * Restore FP context, including the 32 FP data registers and the FP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)  * control & status register, from signal context to the FPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) LEAF(_restore_fp_context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	EX	lw t1, 0(a1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)     defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.set	push
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	SET_HARDFLOAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	.set	mips32r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	.set	fp=64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	mfc0	t0, CP0_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	sll	t0, t0, 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	bgez	t0, 1f			# skip loading odd if FR=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	EX	ldc1 $f1, 8(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	EX	ldc1 $f3, 24(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	EX	ldc1 $f5, 40(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	EX	ldc1 $f7, 56(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	EX	ldc1 $f9, 72(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	EX	ldc1 $f11, 88(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	EX	ldc1 $f13, 104(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	EX	ldc1 $f15, 120(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	EX	ldc1 $f17, 136(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	EX	ldc1 $f19, 152(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	EX	ldc1 $f21, 168(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	EX	ldc1 $f23, 184(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	EX	ldc1 $f25, 200(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	EX	ldc1 $f27, 216(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	EX	ldc1 $f29, 232(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	EX	ldc1 $f31, 248(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 1:	.set pop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	.set push
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	SET_HARDFLOAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	EX	ldc1 $f0, 0(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	EX	ldc1 $f2, 16(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	EX	ldc1 $f4, 32(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	EX	ldc1 $f6, 48(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	EX	ldc1 $f8, 64(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	EX	ldc1 $f10, 80(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	EX	ldc1 $f12, 96(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	EX	ldc1 $f14, 112(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	EX	ldc1 $f16, 128(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	EX	ldc1 $f18, 144(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	EX	ldc1 $f20, 160(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	EX	ldc1 $f22, 176(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	EX	ldc1 $f24, 192(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	EX	ldc1 $f26, 208(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	EX	ldc1 $f28, 224(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	EX	ldc1 $f30, 240(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	ctc1	t1, fcr31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	.set pop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	jr	ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	 li	v0, 0					# success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	END(_restore_fp_context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #ifdef CONFIG_CPU_HAS_MSA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	.macro	op_one_wr	op, idx, base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	.align	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) \idx:	\op	\idx, 0, \base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	jr	ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	.macro	op_msa_wr	name, op
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) LEAF(\name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	.set		push
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	.set		noreorder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	sll		t0, a0, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	PTR_LA		t1, 0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	PTR_ADDU	t0, t0, t1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	jr		t0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	  nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	op_one_wr	\op, 0, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	op_one_wr	\op, 1, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	op_one_wr	\op, 2, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	op_one_wr	\op, 3, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	op_one_wr	\op, 4, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	op_one_wr	\op, 5, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	op_one_wr	\op, 6, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	op_one_wr	\op, 7, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	op_one_wr	\op, 8, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	op_one_wr	\op, 9, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	op_one_wr	\op, 10, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	op_one_wr	\op, 11, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	op_one_wr	\op, 12, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	op_one_wr	\op, 13, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	op_one_wr	\op, 14, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	op_one_wr	\op, 15, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	op_one_wr	\op, 16, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	op_one_wr	\op, 17, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	op_one_wr	\op, 18, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	op_one_wr	\op, 19, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	op_one_wr	\op, 20, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	op_one_wr	\op, 21, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	op_one_wr	\op, 22, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	op_one_wr	\op, 23, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	op_one_wr	\op, 24, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	op_one_wr	\op, 25, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	op_one_wr	\op, 26, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	op_one_wr	\op, 27, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	op_one_wr	\op, 28, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	op_one_wr	\op, 29, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	op_one_wr	\op, 30, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	op_one_wr	\op, 31, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	.set		pop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	END(\name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	op_msa_wr	read_msa_wr_b, st_b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	op_msa_wr	read_msa_wr_h, st_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	op_msa_wr	read_msa_wr_w, st_w
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	op_msa_wr	read_msa_wr_d, st_d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	op_msa_wr	write_msa_wr_b, ld_b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	op_msa_wr	write_msa_wr_h, ld_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	op_msa_wr	write_msa_wr_w, ld_w
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	op_msa_wr	write_msa_wr_d, ld_d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #endif /* CONFIG_CPU_HAS_MSA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #ifdef CONFIG_CPU_HAS_MSA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	.macro	save_msa_upper	wr, off, base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	.set	push
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	.set	noat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	copy_s_d \wr, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	EX sd	$1, \off(\base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #elif defined(CONFIG_CPU_LITTLE_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	copy_s_w \wr, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	EX sw	$1, \off(\base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	copy_s_w \wr, 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	EX sw	$1, (\off+4)(\base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #else /* CONFIG_CPU_BIG_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	copy_s_w \wr, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	EX sw	$1, (\off+4)(\base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	copy_s_w \wr, 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	EX sw	$1, \off(\base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	.set	pop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) LEAF(_save_msa_all_upper)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	save_msa_upper	0, 0x00, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	save_msa_upper	1, 0x08, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	save_msa_upper	2, 0x10, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	save_msa_upper	3, 0x18, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	save_msa_upper	4, 0x20, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	save_msa_upper	5, 0x28, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	save_msa_upper	6, 0x30, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	save_msa_upper	7, 0x38, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	save_msa_upper	8, 0x40, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	save_msa_upper	9, 0x48, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	save_msa_upper	10, 0x50, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	save_msa_upper	11, 0x58, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	save_msa_upper	12, 0x60, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	save_msa_upper	13, 0x68, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	save_msa_upper	14, 0x70, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	save_msa_upper	15, 0x78, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	save_msa_upper	16, 0x80, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	save_msa_upper	17, 0x88, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	save_msa_upper	18, 0x90, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	save_msa_upper	19, 0x98, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	save_msa_upper	20, 0xa0, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	save_msa_upper	21, 0xa8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	save_msa_upper	22, 0xb0, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	save_msa_upper	23, 0xb8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	save_msa_upper	24, 0xc0, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	save_msa_upper	25, 0xc8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	save_msa_upper	26, 0xd0, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	save_msa_upper	27, 0xd8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	save_msa_upper	28, 0xe0, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	save_msa_upper	29, 0xe8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	save_msa_upper	30, 0xf0, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	save_msa_upper	31, 0xf8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	jr	ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	 li	v0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	END(_save_msa_all_upper)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	.macro	restore_msa_upper	wr, off, base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	.set	push
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	.set	noat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	EX ld	$1, \off(\base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	insert_d \wr, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #elif defined(CONFIG_CPU_LITTLE_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	EX lw	$1, \off(\base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	insert_w \wr, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	EX lw	$1, (\off+4)(\base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	insert_w \wr, 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #else /* CONFIG_CPU_BIG_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	EX lw	$1, (\off+4)(\base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	insert_w \wr, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	EX lw	$1, \off(\base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	insert_w \wr, 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	.set	pop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) LEAF(_restore_msa_all_upper)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	restore_msa_upper	0, 0x00, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	restore_msa_upper	1, 0x08, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	restore_msa_upper	2, 0x10, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	restore_msa_upper	3, 0x18, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	restore_msa_upper	4, 0x20, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	restore_msa_upper	5, 0x28, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	restore_msa_upper	6, 0x30, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	restore_msa_upper	7, 0x38, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	restore_msa_upper	8, 0x40, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	restore_msa_upper	9, 0x48, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	restore_msa_upper	10, 0x50, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	restore_msa_upper	11, 0x58, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	restore_msa_upper	12, 0x60, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	restore_msa_upper	13, 0x68, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	restore_msa_upper	14, 0x70, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	restore_msa_upper	15, 0x78, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	restore_msa_upper	16, 0x80, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	restore_msa_upper	17, 0x88, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	restore_msa_upper	18, 0x90, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	restore_msa_upper	19, 0x98, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	restore_msa_upper	20, 0xa0, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	restore_msa_upper	21, 0xa8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	restore_msa_upper	22, 0xb0, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	restore_msa_upper	23, 0xb8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	restore_msa_upper	24, 0xc0, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	restore_msa_upper	25, 0xc8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	restore_msa_upper	26, 0xd0, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	restore_msa_upper	27, 0xd8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	restore_msa_upper	28, 0xe0, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	restore_msa_upper	29, 0xe8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	restore_msa_upper	30, 0xf0, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	restore_msa_upper	31, 0xf8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	jr	ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	 li	v0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	END(_restore_msa_all_upper)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #endif /* CONFIG_CPU_HAS_MSA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	.set	reorder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	.type	fault, @function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	.ent	fault
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) fault:	li	v0, -EFAULT				# failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	jr	ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	.end	fault