^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1992 Ross Biro
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) Linus Torvalds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 1996 David S. Miller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 1999 MIPS Technologies, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 2000 Ulf Carlsson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * At this time Linux/MIPS64 only supports syscall tracing, even for 32-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * binaries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/context_tracking.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/elf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/sched/task_stack.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/regset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/security.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/tracehook.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/audit.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/seccomp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/ftrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/cpu-info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/dsp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <asm/fpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <asm/mipsmtregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <asm/syscall.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <asm/bootinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <asm/reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CREATE_TRACE_POINTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <trace/events/syscalls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * Called by kernel/ptrace.c when detaching..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Make sure single step bits etc are not set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) void ptrace_disable(struct task_struct *child)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Don't load the watchpoint registers for the ex-child. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Read a general register set. We always use the 64-bit format, even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * for 32-bit kernels and for 32-bit processes on a 64-bit kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * Registers are sign extended to fill the available space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int ptrace_getregs(struct task_struct *child, struct user_pt_regs __user *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct pt_regs *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (!access_ok(data, 38 * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) regs = task_pt_regs(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) for (i = 0; i < 32; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) __put_user((long)regs->regs[i], (__s64 __user *)&data->regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) __put_user((long)regs->lo, (__s64 __user *)&data->lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) __put_user((long)regs->hi, (__s64 __user *)&data->hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) __put_user((long)regs->cp0_epc, (__s64 __user *)&data->cp0_epc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __put_user((long)regs->cp0_badvaddr, (__s64 __user *)&data->cp0_badvaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __put_user((long)regs->cp0_status, (__s64 __user *)&data->cp0_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) __put_user((long)regs->cp0_cause, (__s64 __user *)&data->cp0_cause);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Write a general register set. As for PTRACE_GETREGS, we always use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * the 64-bit format. On a 32-bit kernel only the lower order half
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * (according to endianness) will be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int ptrace_setregs(struct task_struct *child, struct user_pt_regs __user *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct pt_regs *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (!access_ok(data, 38 * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) regs = task_pt_regs(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) for (i = 0; i < 32; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) __get_user(regs->regs[i], (__s64 __user *)&data->regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) __get_user(regs->lo, (__s64 __user *)&data->lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) __get_user(regs->hi, (__s64 __user *)&data->hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) __get_user(regs->cp0_epc, (__s64 __user *)&data->cp0_epc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* badvaddr, status, and cause may not be written. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* System call number may have been changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) mips_syscall_update_nr(child, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int ptrace_get_watch_regs(struct task_struct *child,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct pt_watch_regs __user *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) enum pt_watch_style style;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (!cpu_has_watch || boot_cpu_data.watch_reg_use_cnt == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (!access_ok(addr, sizeof(struct pt_watch_regs)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #ifdef CONFIG_32BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) style = pt_watch_style_mips32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define WATCH_STYLE mips32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) style = pt_watch_style_mips64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define WATCH_STYLE mips64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) __put_user(style, &addr->style);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) __put_user(boot_cpu_data.watch_reg_use_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) &addr->WATCH_STYLE.num_valid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) __put_user(child->thread.watch.mips3264.watchlo[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) &addr->WATCH_STYLE.watchlo[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) __put_user(child->thread.watch.mips3264.watchhi[i] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) (MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) &addr->WATCH_STYLE.watchhi[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) __put_user(boot_cpu_data.watch_reg_masks[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) &addr->WATCH_STYLE.watch_masks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) for (; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) __put_user(0, &addr->WATCH_STYLE.watchlo[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) __put_user(0, &addr->WATCH_STYLE.watchhi[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) __put_user(0, &addr->WATCH_STYLE.watch_masks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int ptrace_set_watch_regs(struct task_struct *child,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct pt_watch_regs __user *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int watch_active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned long lt[NUM_WATCH_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u16 ht[NUM_WATCH_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (!cpu_has_watch || boot_cpu_data.watch_reg_use_cnt == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (!access_ok(addr, sizeof(struct pt_watch_regs)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Check the values. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) __get_user(lt[i], &addr->WATCH_STYLE.watchlo[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #ifdef CONFIG_32BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (lt[i] & __UA_LIMIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (test_tsk_thread_flag(child, TIF_32BIT_ADDR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (lt[i] & 0xffffffff80000000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (lt[i] & __UA_LIMIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) __get_user(ht[i], &addr->WATCH_STYLE.watchhi[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (ht[i] & ~MIPS_WATCHHI_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Install them. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (lt[i] & MIPS_WATCHLO_IRW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) watch_active = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) child->thread.watch.mips3264.watchlo[i] = lt[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Set the G bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) child->thread.watch.mips3264.watchhi[i] = ht[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (watch_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) set_tsk_thread_flag(child, TIF_LOAD_WATCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* regset get/set implementations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int gpr32_get(struct task_struct *target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) const struct user_regset *regset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct membuf to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct pt_regs *regs = task_pt_regs(target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 uregs[ELF_NGREG] = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) mips_dump_regs32(uregs, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return membuf_write(&to, uregs, sizeof(uregs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int gpr32_set(struct task_struct *target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) const struct user_regset *regset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned int pos, unsigned int count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) const void *kbuf, const void __user *ubuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct pt_regs *regs = task_pt_regs(target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 uregs[ELF_NGREG];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned start, num_regs, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) start = pos / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) num_regs = count / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (start + num_regs > ELF_NGREG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, uregs, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) sizeof(uregs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) for (i = start; i < num_regs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * Cast all values to signed here so that if this is a 64-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * kernel, the supplied 32-bit values will be sign extended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) switch (i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) case MIPS32_EF_R1 ... MIPS32_EF_R25:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* k0/k1 are ignored. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) case MIPS32_EF_R28 ... MIPS32_EF_R31:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) regs->regs[i - MIPS32_EF_R0] = (s32)uregs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) case MIPS32_EF_LO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) regs->lo = (s32)uregs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) case MIPS32_EF_HI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) regs->hi = (s32)uregs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) case MIPS32_EF_CP0_EPC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) regs->cp0_epc = (s32)uregs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* System call number may have been changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) mips_syscall_update_nr(target, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int gpr64_get(struct task_struct *target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) const struct user_regset *regset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct membuf to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct pt_regs *regs = task_pt_regs(target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u64 uregs[ELF_NGREG] = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) mips_dump_regs64(uregs, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return membuf_write(&to, uregs, sizeof(uregs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int gpr64_set(struct task_struct *target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) const struct user_regset *regset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned int pos, unsigned int count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) const void *kbuf, const void __user *ubuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct pt_regs *regs = task_pt_regs(target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u64 uregs[ELF_NGREG];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) unsigned start, num_regs, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) start = pos / sizeof(u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) num_regs = count / sizeof(u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (start + num_regs > ELF_NGREG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, uregs, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) sizeof(uregs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) for (i = start; i < num_regs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) switch (i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) case MIPS64_EF_R1 ... MIPS64_EF_R25:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* k0/k1 are ignored. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) case MIPS64_EF_R28 ... MIPS64_EF_R31:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) regs->regs[i - MIPS64_EF_R0] = uregs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) case MIPS64_EF_LO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) regs->lo = uregs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) case MIPS64_EF_HI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) regs->hi = uregs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) case MIPS64_EF_CP0_EPC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) regs->cp0_epc = uregs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* System call number may have been changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) mips_syscall_update_nr(target, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #endif /* CONFIG_64BIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #ifdef CONFIG_MIPS_FP_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * Poke at FCSR according to its mask. Set the Cause bits even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * if a corresponding Enable bit is set. This will be noticed at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * the time the thread is switched to and SIGFPE thrown accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static void ptrace_setfcr31(struct task_struct *child, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u32 fcr31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) fcr31 = child->thread.fpu.fcr31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) mask = boot_cpu_data.fpu_msk31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) child->thread.fpu.fcr31 = (value & ~mask) | (fcr31 & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) int ptrace_getfpregs(struct task_struct *child, __u32 __user *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (!access_ok(data, 33 * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (tsk_used_math(child)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) union fpureg *fregs = get_fpu_regs(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) for (i = 0; i < 32; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) __put_user(get_fpr64(&fregs[i], 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) i + (__u64 __user *)data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) for (i = 0; i < 32; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) __put_user((__u64) -1, i + (__u64 __user *) data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) __put_user(child->thread.fpu.fcr31, data + 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) __put_user(boot_cpu_data.fpu_id, data + 65);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) union fpureg *fregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u64 fpr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (!access_ok(data, 33 * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) init_fp_ctx(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) fregs = get_fpu_regs(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) for (i = 0; i < 32; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) __get_user(fpr_val, i + (__u64 __user *)data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) set_fpr64(&fregs[i], 0, fpr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) __get_user(value, data + 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ptrace_setfcr31(child, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* FIR may not be written. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * Copy the floating-point context to the supplied NT_PRFPREG buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * !CONFIG_CPU_HAS_MSA variant. FP context's general register slots
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * correspond 1:1 to buffer slots. Only general registers are copied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static void fpr_get_fpa(struct task_struct *target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct membuf *to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) membuf_write(to, &target->thread.fpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) NUM_FPU_REGS * sizeof(elf_fpreg_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * Copy the floating-point context to the supplied NT_PRFPREG buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * CONFIG_CPU_HAS_MSA variant. Only lower 64 bits of FP context's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * general register slots are copied to buffer slots. Only general
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * registers are copied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static void fpr_get_msa(struct task_struct *target, struct membuf *to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) BUILD_BUG_ON(sizeof(u64) != sizeof(elf_fpreg_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) for (i = 0; i < NUM_FPU_REGS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) membuf_store(to, get_fpr64(&target->thread.fpu.fpr[i], 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * Copy the floating-point context to the supplied NT_PRFPREG buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * Choose the appropriate helper for general registers, and then copy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * the FCSR and FIR registers separately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static int fpr_get(struct task_struct *target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) const struct user_regset *regset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct membuf to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (sizeof(target->thread.fpu.fpr[0]) == sizeof(elf_fpreg_t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) fpr_get_fpa(target, &to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) fpr_get_msa(target, &to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) membuf_write(&to, &target->thread.fpu.fcr31, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) membuf_write(&to, &boot_cpu_data.fpu_id, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * Copy the supplied NT_PRFPREG buffer to the floating-point context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * !CONFIG_CPU_HAS_MSA variant. Buffer slots correspond 1:1 to FP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * context's general register slots. Only general registers are copied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static int fpr_set_fpa(struct task_struct *target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) unsigned int *pos, unsigned int *count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) const void **kbuf, const void __user **ubuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return user_regset_copyin(pos, count, kbuf, ubuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) &target->thread.fpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 0, NUM_FPU_REGS * sizeof(elf_fpreg_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * Copy the supplied NT_PRFPREG buffer to the floating-point context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * CONFIG_CPU_HAS_MSA variant. Buffer slots are copied to lower 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * bits only of FP context's general register slots. Only general
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * registers are copied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static int fpr_set_msa(struct task_struct *target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) unsigned int *pos, unsigned int *count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) const void **kbuf, const void __user **ubuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u64 fpr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) BUILD_BUG_ON(sizeof(fpr_val) != sizeof(elf_fpreg_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) for (i = 0; i < NUM_FPU_REGS && *count > 0; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) err = user_regset_copyin(pos, count, kbuf, ubuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) &fpr_val, i * sizeof(elf_fpreg_t),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) (i + 1) * sizeof(elf_fpreg_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) set_fpr64(&target->thread.fpu.fpr[i], 0, fpr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * Copy the supplied NT_PRFPREG buffer to the floating-point context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * Choose the appropriate helper for general registers, and then copy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * the FCSR register separately. Ignore the incoming FIR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * contents though, as the register is read-only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * We optimize for the case where `count % sizeof(elf_fpreg_t) == 0',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * which is supposed to have been guaranteed by the kernel before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * calling us, e.g. in `ptrace_regset'. We enforce that requirement,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * so that we can safely avoid preinitializing temporaries for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * partial register writes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int fpr_set(struct task_struct *target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) const struct user_regset *regset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) unsigned int pos, unsigned int count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) const void *kbuf, const void __user *ubuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) const int fcr31_pos = NUM_FPU_REGS * sizeof(elf_fpreg_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) const int fir_pos = fcr31_pos + sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) u32 fcr31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) BUG_ON(count % sizeof(elf_fpreg_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (pos + count > sizeof(elf_fpregset_t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) init_fp_ctx(target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (sizeof(target->thread.fpu.fpr[0]) == sizeof(elf_fpreg_t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) err = fpr_set_fpa(target, &pos, &count, &kbuf, &ubuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) err = fpr_set_msa(target, &pos, &count, &kbuf, &ubuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (count > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) err = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) &fcr31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) fcr31_pos, fcr31_pos + sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ptrace_setfcr31(target, fcr31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (count > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) err = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) fir_pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) fir_pos + sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* Copy the FP mode setting to the supplied NT_MIPS_FP_MODE buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static int fp_mode_get(struct task_struct *target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) const struct user_regset *regset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct membuf to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return membuf_store(&to, (int)mips_get_process_fp_mode(target));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * Copy the supplied NT_MIPS_FP_MODE buffer to the FP mode setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * We optimize for the case where `count % sizeof(int) == 0', which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * is supposed to have been guaranteed by the kernel before calling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * us, e.g. in `ptrace_regset'. We enforce that requirement, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * that we can safely avoid preinitializing temporaries for partial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * mode writes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static int fp_mode_set(struct task_struct *target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) const struct user_regset *regset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) unsigned int pos, unsigned int count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) const void *kbuf, const void __user *ubuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) int fp_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) BUG_ON(count % sizeof(int));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (pos + count > sizeof(fp_mode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &fp_mode, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) sizeof(fp_mode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (count > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) err = mips_set_process_fp_mode(target, fp_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #endif /* CONFIG_MIPS_FP_SUPPORT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #ifdef CONFIG_CPU_HAS_MSA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct msa_control_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) unsigned int fir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) unsigned int fcsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) unsigned int msair;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) unsigned int msacsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static void copy_pad_fprs(struct task_struct *target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) const struct user_regset *regset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) struct membuf *to,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) unsigned int live_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) unsigned long long fill = ~0ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) unsigned int cp_sz, pad_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) cp_sz = min(regset->size, live_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) pad_sz = regset->size - cp_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) WARN_ON(pad_sz % sizeof(fill));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) for (i = 0; i < NUM_FPU_REGS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) membuf_write(to, &target->thread.fpu.fpr[i], cp_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) for (j = 0; j < (pad_sz / sizeof(fill)); j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) membuf_store(to, fill);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static int msa_get(struct task_struct *target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) const struct user_regset *regset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct membuf to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) const unsigned int wr_size = NUM_FPU_REGS * regset->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) const struct msa_control_regs ctrl_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .fir = boot_cpu_data.fpu_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .fcsr = target->thread.fpu.fcr31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .msair = boot_cpu_data.msa_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .msacsr = target->thread.fpu.msacsr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (!tsk_used_math(target)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* The task hasn't used FP or MSA, fill with 0xff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) copy_pad_fprs(target, regset, &to, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) } else if (!test_tsk_thread_flag(target, TIF_MSA_CTX_LIVE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* Copy scalar FP context, fill the rest with 0xff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) copy_pad_fprs(target, regset, &to, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) } else if (sizeof(target->thread.fpu.fpr[0]) == regset->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* Trivially copy the vector registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) membuf_write(&to, &target->thread.fpu.fpr, wr_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /* Copy as much context as possible, fill the rest with 0xff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) copy_pad_fprs(target, regset, &to,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) sizeof(target->thread.fpu.fpr[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return membuf_write(&to, &ctrl_regs, sizeof(ctrl_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static int msa_set(struct task_struct *target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) const struct user_regset *regset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) unsigned int pos, unsigned int count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) const void *kbuf, const void __user *ubuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) const unsigned int wr_size = NUM_FPU_REGS * regset->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct msa_control_regs ctrl_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) unsigned int cp_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) int i, err, start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) init_fp_ctx(target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (sizeof(target->thread.fpu.fpr[0]) == regset->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* Trivially copy the vector registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) err = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) &target->thread.fpu.fpr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 0, wr_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /* Copy as much context as possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) cp_sz = min_t(unsigned int, regset->size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) sizeof(target->thread.fpu.fpr[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) i = start = err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) for (; i < NUM_FPU_REGS; i++, start += regset->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) err |= user_regset_copyin(&pos, &count, &kbuf, &ubuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) &target->thread.fpu.fpr[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) start, start + cp_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &ctrl_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) wr_size, wr_size + sizeof(ctrl_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) target->thread.fpu.fcr31 = ctrl_regs.fcsr & ~FPU_CSR_ALL_X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) target->thread.fpu.msacsr = ctrl_regs.msacsr & ~MSA_CSR_CAUSEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #endif /* CONFIG_CPU_HAS_MSA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * Copy the DSP context to the supplied 32-bit NT_MIPS_DSP buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static int dsp32_get(struct task_struct *target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) const struct user_regset *regset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct membuf to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) u32 dspregs[NUM_DSP_REGS + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) BUG_ON(to.left % sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (!cpu_has_dsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) for (i = 0; i < NUM_DSP_REGS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) dspregs[i] = target->thread.dsp.dspr[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) dspregs[NUM_DSP_REGS] = target->thread.dsp.dspcontrol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return membuf_write(&to, dspregs, sizeof(dspregs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * Copy the supplied 32-bit NT_MIPS_DSP buffer to the DSP context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static int dsp32_set(struct task_struct *target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) const struct user_regset *regset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) unsigned int pos, unsigned int count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) const void *kbuf, const void __user *ubuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) unsigned int start, num_regs, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) u32 dspregs[NUM_DSP_REGS + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) BUG_ON(count % sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (!cpu_has_dsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) start = pos / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) num_regs = count / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (start + num_regs > NUM_DSP_REGS + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, dspregs, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) sizeof(dspregs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) for (i = start; i < num_regs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) switch (i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) case 0 ... NUM_DSP_REGS - 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) target->thread.dsp.dspr[i] = (s32)dspregs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) case NUM_DSP_REGS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) target->thread.dsp.dspcontrol = (s32)dspregs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * Copy the DSP context to the supplied 64-bit NT_MIPS_DSP buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static int dsp64_get(struct task_struct *target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) const struct user_regset *regset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) struct membuf to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) u64 dspregs[NUM_DSP_REGS + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) BUG_ON(to.left % sizeof(u64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (!cpu_has_dsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) for (i = 0; i < NUM_DSP_REGS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) dspregs[i] = target->thread.dsp.dspr[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) dspregs[NUM_DSP_REGS] = target->thread.dsp.dspcontrol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) return membuf_write(&to, dspregs, sizeof(dspregs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * Copy the supplied 64-bit NT_MIPS_DSP buffer to the DSP context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static int dsp64_set(struct task_struct *target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) const struct user_regset *regset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) unsigned int pos, unsigned int count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) const void *kbuf, const void __user *ubuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) unsigned int start, num_regs, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) u64 dspregs[NUM_DSP_REGS + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) BUG_ON(count % sizeof(u64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (!cpu_has_dsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) start = pos / sizeof(u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) num_regs = count / sizeof(u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (start + num_regs > NUM_DSP_REGS + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, dspregs, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) sizeof(dspregs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) for (i = start; i < num_regs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) switch (i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) case 0 ... NUM_DSP_REGS - 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) target->thread.dsp.dspr[i] = dspregs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) case NUM_DSP_REGS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) target->thread.dsp.dspcontrol = dspregs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #endif /* CONFIG_64BIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) * Determine whether the DSP context is present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static int dsp_active(struct task_struct *target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) const struct user_regset *regset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return cpu_has_dsp ? NUM_DSP_REGS + 1 : -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) enum mips_regset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) REGSET_GPR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) REGSET_DSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #ifdef CONFIG_MIPS_FP_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) REGSET_FPR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) REGSET_FP_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #ifdef CONFIG_CPU_HAS_MSA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) REGSET_MSA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) struct pt_regs_offset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define REG_OFFSET_NAME(reg, r) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .name = #reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .offset = offsetof(struct pt_regs, r) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define REG_OFFSET_END { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .name = NULL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .offset = 0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static const struct pt_regs_offset regoffset_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) REG_OFFSET_NAME(r0, regs[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) REG_OFFSET_NAME(r1, regs[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) REG_OFFSET_NAME(r2, regs[2]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) REG_OFFSET_NAME(r3, regs[3]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) REG_OFFSET_NAME(r4, regs[4]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) REG_OFFSET_NAME(r5, regs[5]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) REG_OFFSET_NAME(r6, regs[6]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) REG_OFFSET_NAME(r7, regs[7]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) REG_OFFSET_NAME(r8, regs[8]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) REG_OFFSET_NAME(r9, regs[9]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) REG_OFFSET_NAME(r10, regs[10]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) REG_OFFSET_NAME(r11, regs[11]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) REG_OFFSET_NAME(r12, regs[12]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) REG_OFFSET_NAME(r13, regs[13]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) REG_OFFSET_NAME(r14, regs[14]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) REG_OFFSET_NAME(r15, regs[15]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) REG_OFFSET_NAME(r16, regs[16]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) REG_OFFSET_NAME(r17, regs[17]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) REG_OFFSET_NAME(r18, regs[18]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) REG_OFFSET_NAME(r19, regs[19]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) REG_OFFSET_NAME(r20, regs[20]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) REG_OFFSET_NAME(r21, regs[21]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) REG_OFFSET_NAME(r22, regs[22]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) REG_OFFSET_NAME(r23, regs[23]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) REG_OFFSET_NAME(r24, regs[24]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) REG_OFFSET_NAME(r25, regs[25]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) REG_OFFSET_NAME(r26, regs[26]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) REG_OFFSET_NAME(r27, regs[27]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) REG_OFFSET_NAME(r28, regs[28]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) REG_OFFSET_NAME(r29, regs[29]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) REG_OFFSET_NAME(r30, regs[30]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) REG_OFFSET_NAME(r31, regs[31]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) REG_OFFSET_NAME(c0_status, cp0_status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) REG_OFFSET_NAME(hi, hi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) REG_OFFSET_NAME(lo, lo),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #ifdef CONFIG_CPU_HAS_SMARTMIPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) REG_OFFSET_NAME(acx, acx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) REG_OFFSET_NAME(c0_badvaddr, cp0_badvaddr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) REG_OFFSET_NAME(c0_cause, cp0_cause),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) REG_OFFSET_NAME(c0_epc, cp0_epc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #ifdef CONFIG_CPU_CAVIUM_OCTEON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) REG_OFFSET_NAME(mpl0, mpl[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) REG_OFFSET_NAME(mpl1, mpl[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) REG_OFFSET_NAME(mpl2, mpl[2]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) REG_OFFSET_NAME(mtp0, mtp[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) REG_OFFSET_NAME(mtp1, mtp[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) REG_OFFSET_NAME(mtp2, mtp[2]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) REG_OFFSET_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * regs_query_register_offset() - query register offset from its name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) * @name: the name of a register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * regs_query_register_offset() returns the offset of a register in struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * pt_regs from its name. If the name is invalid, this returns -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) int regs_query_register_offset(const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) const struct pt_regs_offset *roff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) for (roff = regoffset_table; roff->name != NULL; roff++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (!strcmp(roff->name, name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) return roff->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) static const struct user_regset mips_regsets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) [REGSET_GPR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .core_note_type = NT_PRSTATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .n = ELF_NGREG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .size = sizeof(unsigned int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .align = sizeof(unsigned int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .regset_get = gpr32_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .set = gpr32_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) [REGSET_DSP] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .core_note_type = NT_MIPS_DSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .n = NUM_DSP_REGS + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .size = sizeof(u32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .align = sizeof(u32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .regset_get = dsp32_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .set = dsp32_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .active = dsp_active,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #ifdef CONFIG_MIPS_FP_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) [REGSET_FPR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .core_note_type = NT_PRFPREG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .n = ELF_NFPREG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .size = sizeof(elf_fpreg_t),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .align = sizeof(elf_fpreg_t),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .regset_get = fpr_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .set = fpr_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) [REGSET_FP_MODE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .core_note_type = NT_MIPS_FP_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .n = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .size = sizeof(int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .align = sizeof(int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .regset_get = fp_mode_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .set = fp_mode_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #ifdef CONFIG_CPU_HAS_MSA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) [REGSET_MSA] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .core_note_type = NT_MIPS_MSA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .n = NUM_FPU_REGS + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .size = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .align = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .regset_get = msa_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .set = msa_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) static const struct user_regset_view user_mips_view = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .name = "mips",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .e_machine = ELF_ARCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .ei_osabi = ELF_OSABI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .regsets = mips_regsets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .n = ARRAY_SIZE(mips_regsets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) static const struct user_regset mips64_regsets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) [REGSET_GPR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .core_note_type = NT_PRSTATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .n = ELF_NGREG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .size = sizeof(unsigned long),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .align = sizeof(unsigned long),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .regset_get = gpr64_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .set = gpr64_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) [REGSET_DSP] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .core_note_type = NT_MIPS_DSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .n = NUM_DSP_REGS + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .size = sizeof(u64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .align = sizeof(u64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .regset_get = dsp64_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .set = dsp64_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .active = dsp_active,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #ifdef CONFIG_MIPS_FP_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) [REGSET_FP_MODE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .core_note_type = NT_MIPS_FP_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .n = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .size = sizeof(int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .align = sizeof(int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .regset_get = fp_mode_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .set = fp_mode_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) [REGSET_FPR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .core_note_type = NT_PRFPREG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .n = ELF_NFPREG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .size = sizeof(elf_fpreg_t),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .align = sizeof(elf_fpreg_t),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .regset_get = fpr_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .set = fpr_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) #ifdef CONFIG_CPU_HAS_MSA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) [REGSET_MSA] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .core_note_type = NT_MIPS_MSA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .n = NUM_FPU_REGS + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .size = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .align = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .regset_get = msa_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .set = msa_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) static const struct user_regset_view user_mips64_view = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .name = "mips64",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .e_machine = ELF_ARCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .ei_osabi = ELF_OSABI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .regsets = mips64_regsets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .n = ARRAY_SIZE(mips64_regsets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) #ifdef CONFIG_MIPS32_N32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static const struct user_regset_view user_mipsn32_view = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .name = "mipsn32",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .e_flags = EF_MIPS_ABI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .e_machine = ELF_ARCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .ei_osabi = ELF_OSABI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .regsets = mips64_regsets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .n = ARRAY_SIZE(mips64_regsets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #endif /* CONFIG_MIPS32_N32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) #endif /* CONFIG_64BIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) const struct user_regset_view *task_user_regset_view(struct task_struct *task)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) #ifdef CONFIG_32BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) return &user_mips_view;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #ifdef CONFIG_MIPS32_O32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if (test_tsk_thread_flag(task, TIF_32BIT_REGS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) return &user_mips_view;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) #ifdef CONFIG_MIPS32_N32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (test_tsk_thread_flag(task, TIF_32BIT_ADDR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) return &user_mipsn32_view;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) return &user_mips64_view;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) long arch_ptrace(struct task_struct *child, long request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) unsigned long addr, unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) void __user *addrp = (void __user *) addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) void __user *datavp = (void __user *) data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) unsigned long __user *datalp = (void __user *) data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) switch (request) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) /* when I and D space are separate, these will need to be fixed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) case PTRACE_PEEKTEXT: /* read word at location addr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) case PTRACE_PEEKDATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) ret = generic_ptrace_peekdata(child, addr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) /* Read the word at location addr in the USER area. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) case PTRACE_PEEKUSR: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) struct pt_regs *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) unsigned long tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) regs = task_pt_regs(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) ret = 0; /* Default return value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) switch (addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) case 0 ... 31:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) tmp = regs->regs[addr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #ifdef CONFIG_MIPS_FP_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) case FPR_BASE ... FPR_BASE + 31: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) union fpureg *fregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (!tsk_used_math(child)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) /* FP not yet used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) tmp = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) fregs = get_fpu_regs(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) #ifdef CONFIG_32BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) * The odd registers are actually the high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) * order bits of the values stored in the even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) * registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) tmp = get_fpr32(&fregs[(addr & ~1) - FPR_BASE],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) addr & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) tmp = get_fpr64(&fregs[addr - FPR_BASE], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) case FPC_CSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) tmp = child->thread.fpu.fcr31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) case FPC_EIR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) /* implementation / version register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) tmp = boot_cpu_data.fpu_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) case PC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) tmp = regs->cp0_epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) case CAUSE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) tmp = regs->cp0_cause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) case BADVADDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) tmp = regs->cp0_badvaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) case MMHI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) tmp = regs->hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) case MMLO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) tmp = regs->lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) #ifdef CONFIG_CPU_HAS_SMARTMIPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) case ACX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) tmp = regs->acx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) case DSP_BASE ... DSP_BASE + 5: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) dspreg_t *dregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) if (!cpu_has_dsp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) dregs = __get_dsp_regs(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) tmp = dregs[addr - DSP_BASE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) case DSP_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (!cpu_has_dsp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) tmp = child->thread.dsp.dspcontrol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) ret = put_user(tmp, datalp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /* when I and D space are separate, this will have to be fixed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) case PTRACE_POKETEXT: /* write the word at location addr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) case PTRACE_POKEDATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) ret = generic_ptrace_pokedata(child, addr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) case PTRACE_POKEUSR: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) struct pt_regs *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) regs = task_pt_regs(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) switch (addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) case 0 ... 31:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) regs->regs[addr] = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) /* System call number may have been changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (addr == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) mips_syscall_update_nr(child, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) else if (addr == 4 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) mips_syscall_is_indirect(child, regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) mips_syscall_update_nr(child, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) #ifdef CONFIG_MIPS_FP_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) case FPR_BASE ... FPR_BASE + 31: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) union fpureg *fregs = get_fpu_regs(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) init_fp_ctx(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) #ifdef CONFIG_32BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) * The odd registers are actually the high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) * order bits of the values stored in the even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) * registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) set_fpr32(&fregs[(addr & ~1) - FPR_BASE],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) addr & 1, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) set_fpr64(&fregs[addr - FPR_BASE], 0, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) case FPC_CSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) init_fp_ctx(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) ptrace_setfcr31(child, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) case PC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) regs->cp0_epc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) case MMHI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) regs->hi = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) case MMLO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) regs->lo = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #ifdef CONFIG_CPU_HAS_SMARTMIPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) case ACX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) regs->acx = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) case DSP_BASE ... DSP_BASE + 5: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) dspreg_t *dregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) if (!cpu_has_dsp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) dregs = __get_dsp_regs(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) dregs[addr - DSP_BASE] = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) case DSP_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (!cpu_has_dsp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) child->thread.dsp.dspcontrol = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) /* The rest are not allowed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) case PTRACE_GETREGS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) ret = ptrace_getregs(child, datavp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) case PTRACE_SETREGS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) ret = ptrace_setregs(child, datavp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) #ifdef CONFIG_MIPS_FP_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) case PTRACE_GETFPREGS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) ret = ptrace_getfpregs(child, datavp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) case PTRACE_SETFPREGS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) ret = ptrace_setfpregs(child, datavp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) case PTRACE_GET_THREAD_AREA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) ret = put_user(task_thread_info(child)->tp_value, datalp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) case PTRACE_GET_WATCH_REGS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) ret = ptrace_get_watch_regs(child, addrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) case PTRACE_SET_WATCH_REGS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) ret = ptrace_set_watch_regs(child, addrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) ret = ptrace_request(child, request, addr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) * Notification of system call entry/exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) * - triggered by current->work.syscall_trace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) asmlinkage long syscall_trace_enter(struct pt_regs *regs, long syscall)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) user_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) current_thread_info()->syscall = syscall;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) if (test_thread_flag(TIF_SYSCALL_TRACE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (tracehook_report_syscall_entry(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) syscall = current_thread_info()->syscall;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) #ifdef CONFIG_SECCOMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) if (unlikely(test_thread_flag(TIF_SECCOMP))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) struct seccomp_data sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) unsigned long args[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) sd.nr = syscall;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) sd.arch = syscall_get_arch(current);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) syscall_get_arguments(current, regs, args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) for (i = 0; i < 6; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) sd.args[i] = args[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) sd.instruction_pointer = KSTK_EIP(current);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) ret = __secure_computing(&sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (ret == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) syscall = current_thread_info()->syscall;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) trace_sys_enter(regs, regs->regs[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) audit_syscall_entry(syscall, regs->regs[4], regs->regs[5],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) regs->regs[6], regs->regs[7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) * Negative syscall numbers are mistaken for rejected syscalls, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) * won't have had the return value set appropriately, so we do so now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (syscall < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) syscall_set_return_value(current, regs, -ENOSYS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) return syscall;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) * Notification of system call entry/exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) * - triggered by current->work.syscall_trace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) asmlinkage void syscall_trace_leave(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) * We may come here right after calling schedule_user()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) * or do_notify_resume(), in which case we can be in RCU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) * user mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) user_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) audit_syscall_exit(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) trace_sys_exit(regs, regs_return_value(regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) if (test_thread_flag(TIF_SYSCALL_TRACE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) tracehook_report_syscall_exit(regs, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) user_enter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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