Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Copyright (C) 1995, 1996, 2001  Ralf Baechle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *  Copyright (C) 2001, 2004  MIPS Technologies, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2004	Maciej W. Rozycki
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <asm/bootinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/cpu-features.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/idle.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) unsigned int vced_count, vcei_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *  * No lock; only written during early bootup by CPU 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  *   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) static RAW_NOTIFIER_HEAD(proc_cpuinfo_chain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) int __ref register_proc_cpuinfo_notifier(struct notifier_block *nb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	return raw_notifier_chain_register(&proc_cpuinfo_chain, nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	return raw_notifier_call_chain(&proc_cpuinfo_chain, val, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static int show_cpuinfo(struct seq_file *m, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	struct proc_cpuinfo_notifier_args proc_cpuinfo_notifier_args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	unsigned long n = (unsigned long) v - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	unsigned int version = cpu_data[n].processor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	unsigned int fp_vers = cpu_data[n].fpu_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	char fmt [64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	if (!cpu_online(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	 * For the first processor also print the system type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	if (n == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		seq_printf(m, "system type\t\t: %s\n", get_system_type());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		if (mips_get_machine_name())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 			seq_printf(m, "machine\t\t\t: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 				   mips_get_machine_name());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	seq_printf(m, "processor\t\t: %ld\n", n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		      cpu_data[n].options & MIPS_CPU_FPU ? "  FPU V%d.%d" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	seq_printf(m, fmt, __cpu_name[n],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		      (version >> 4) & 0x0f, version & 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		      (fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	seq_printf(m, "BogoMIPS\t\t: %u.%02u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		      cpu_data[n].udelay_val / (500000/HZ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		      (cpu_data[n].udelay_val / (5000/HZ)) % 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	seq_printf(m, "microsecond timers\t: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		      cpu_has_counter ? "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	seq_printf(m, "extra interrupt vector\t: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		      cpu_has_divec ? "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	seq_printf(m, "hardware watchpoint\t: %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		      cpu_has_watch ? "yes, " : "no\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	if (cpu_has_watch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		seq_printf(m, "count: %d, address/irw mask: [",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		      cpu_data[n].watch_reg_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		for (i = 0; i < cpu_data[n].watch_reg_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 			seq_printf(m, "%s0x%04x", i ? ", " : "" ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 				cpu_data[n].watch_reg_masks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		seq_printf(m, "]\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	seq_printf(m, "isa\t\t\t:"); 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	if (cpu_has_mips_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		seq_printf(m, " mips1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	if (cpu_has_mips_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		seq_printf(m, "%s", " mips2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	if (cpu_has_mips_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		seq_printf(m, "%s", " mips3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	if (cpu_has_mips_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		seq_printf(m, "%s", " mips4");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	if (cpu_has_mips_5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		seq_printf(m, "%s", " mips5");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	if (cpu_has_mips32r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		seq_printf(m, "%s", " mips32r1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	if (cpu_has_mips32r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		seq_printf(m, "%s", " mips32r2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	if (cpu_has_mips32r5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		seq_printf(m, "%s", " mips32r5");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	if (cpu_has_mips32r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		seq_printf(m, "%s", " mips32r6");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	if (cpu_has_mips64r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		seq_printf(m, "%s", " mips64r1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	if (cpu_has_mips64r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		seq_printf(m, "%s", " mips64r2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	if (cpu_has_mips64r5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		seq_printf(m, "%s", " mips64r5");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	if (cpu_has_mips64r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		seq_printf(m, "%s", " mips64r6");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	seq_printf(m, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	seq_printf(m, "ASEs implemented\t:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (cpu_has_mips16)	seq_printf(m, "%s", " mips16");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	if (cpu_has_mips16e2)	seq_printf(m, "%s", " mips16e2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	if (cpu_has_mdmx)	seq_printf(m, "%s", " mdmx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	if (cpu_has_mips3d)	seq_printf(m, "%s", " mips3d");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (cpu_has_smartmips)	seq_printf(m, "%s", " smartmips");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	if (cpu_has_dsp)	seq_printf(m, "%s", " dsp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	if (cpu_has_dsp2)	seq_printf(m, "%s", " dsp2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	if (cpu_has_dsp3)	seq_printf(m, "%s", " dsp3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	if (cpu_has_mipsmt)	seq_printf(m, "%s", " mt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (cpu_has_mmips)	seq_printf(m, "%s", " micromips");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	if (cpu_has_vz)		seq_printf(m, "%s", " vz");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	if (cpu_has_msa)	seq_printf(m, "%s", " msa");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	if (cpu_has_eva)	seq_printf(m, "%s", " eva");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	if (cpu_has_htw)	seq_printf(m, "%s", " htw");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if (cpu_has_xpa)	seq_printf(m, "%s", " xpa");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	if (cpu_has_loongson_mmi)	seq_printf(m, "%s", " loongson-mmi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	if (cpu_has_loongson_cam)	seq_printf(m, "%s", " loongson-cam");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	if (cpu_has_loongson_ext)	seq_printf(m, "%s", " loongson-ext");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	if (cpu_has_loongson_ext2)	seq_printf(m, "%s", " loongson-ext2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	seq_printf(m, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (cpu_has_mmips) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		seq_printf(m, "micromips kernel\t: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		      (read_c0_config3() & MIPS_CONF3_ISA_OE) ?  "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	seq_printf(m, "shadow register sets\t: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		      cpu_data[n].srsets);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	seq_printf(m, "kscratch registers\t: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		      hweight8(cpu_data[n].kscratch_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	seq_printf(m, "package\t\t\t: %d\n", cpu_data[n].package);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	seq_printf(m, "core\t\t\t: %d\n", cpu_core(&cpu_data[n]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	if (cpu_has_mipsmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		seq_printf(m, "VPE\t\t\t: %d\n", cpu_vpe_id(&cpu_data[n]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	else if (cpu_has_vp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		seq_printf(m, "VP\t\t\t: %d\n", cpu_vpe_id(&cpu_data[n]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		      cpu_has_vce ? "%u" : "not available");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	seq_printf(m, fmt, 'D', vced_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	seq_printf(m, fmt, 'I', vcei_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	proc_cpuinfo_notifier_args.m = m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	proc_cpuinfo_notifier_args.n = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	raw_notifier_call_chain(&proc_cpuinfo_chain, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 				&proc_cpuinfo_notifier_args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	seq_printf(m, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static void *c_start(struct seq_file *m, loff_t *pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	unsigned long i = *pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	return i < NR_CPUS ? (void *) (i + 1) : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static void *c_next(struct seq_file *m, void *v, loff_t *pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	++*pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	return c_start(m, pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static void c_stop(struct seq_file *m, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) const struct seq_operations cpuinfo_op = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	.start	= c_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	.next	= c_next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	.stop	= c_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	.show	= show_cpuinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };