^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2016 Imagination Technologies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Marcin Nowakowski <marcin.nowakowski@mips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __PROBES_COMMON_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __PROBES_COMMON_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/inst.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) int __insn_is_compact_branch(union mips_instruction insn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) static inline int __insn_has_delay_slot(const union mips_instruction insn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) switch (insn.i_format.opcode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * jr and jalr are in r_format format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) case spec_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) switch (insn.r_format.func) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) case jalr_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) case jr_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * This group contains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * bltz_op, bgez_op, bltzl_op, bgezl_op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) case bcond_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) switch (insn.i_format.rt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) case bltz_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) case bltzl_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) case bgez_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) case bgezl_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) case bltzal_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) case bltzall_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) case bgezal_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) case bgezall_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) case bposge32_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * These are unconditional and in j_format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) case jal_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) case j_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) case beq_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) case beql_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) case bne_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) case bnel_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) case blez_op: /* not really i_format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) case blezl_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) case bgtz_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) case bgtzl_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * And now the FPA/cp1 branch instructions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) case cop1_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #ifdef CONFIG_CPU_CAVIUM_OCTEON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) case lwc2_op: /* This is bbit0 on Octeon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) case ldc2_op: /* This is bbit032 on Octeon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) case swc2_op: /* This is bbit1 on Octeon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) case sdc2_op: /* This is bbit132 on Octeon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #endif /* __PROBES_COMMON_H */