^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2014 Imagination Technologies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Paul Burton <paul.burton@mips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/cpuhotplug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/percpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/cacheops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/idle.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/mips-cps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/mipsmtregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/pm-cps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/smp-cps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/uasm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * cps_nc_entry_fn - type of a generated non-coherent state entry function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * @online: the count of online coupled VPEs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * @nc_ready_count: pointer to a non-coherent mapping of the core ready_count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * The code entering & exiting non-coherent states is generated at runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * using uasm, in order to ensure that the compiler cannot insert a stray
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * memory access at an unfortunate time and to allow the generation of optimal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * core-specific code particularly for cache routines. If coupled_coherence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * is non-zero and this is the entry function for the CPS_PM_NC_WAIT state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * returns the number of VPEs that were in the wait state at the point this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * VPE left it. Returns garbage if coupled_coherence is zero or this is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * the entry function for CPS_PM_NC_WAIT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) typedef unsigned (*cps_nc_entry_fn)(unsigned online, u32 *nc_ready_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * The entry point of the generated non-coherent idle state entry/exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * functions. Actually per-core rather than per-CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static DEFINE_PER_CPU_READ_MOSTLY(cps_nc_entry_fn[CPS_PM_STATE_COUNT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) nc_asm_enter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Bitmap indicating which states are supported by the system */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static DECLARE_BITMAP(state_support, CPS_PM_STATE_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Indicates the number of coupled VPEs ready to operate in a non-coherent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * state. Actually per-core rather than per-CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static DEFINE_PER_CPU_ALIGNED(u32*, ready_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Indicates online CPUs coupled with the current CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static DEFINE_PER_CPU_ALIGNED(cpumask_t, online_coupled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * Used to synchronize entry to deep idle states. Actually per-core rather
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * than per-CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static DEFINE_PER_CPU_ALIGNED(atomic_t, pm_barrier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Saved CPU state across the CPS_PM_POWER_GATED state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) DEFINE_PER_CPU_ALIGNED(struct mips_static_suspend_state, cps_cpu_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* A somewhat arbitrary number of labels & relocs for uasm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static struct uasm_label labels[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static struct uasm_reloc relocs[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) enum mips_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) zero, at, v0, v1, a0, a1, a2, a3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) t0, t1, t2, t3, t4, t5, t6, t7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) s0, s1, s2, s3, s4, s5, s6, s7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) t8, t9, k0, k1, gp, sp, fp, ra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) bool cps_pm_support_state(enum cps_pm_state state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return test_bit(state, state_support);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static void coupled_barrier(atomic_t *a, unsigned online)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * This function is effectively the same as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * cpuidle_coupled_parallel_barrier, which can't be used here since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * there's no cpuidle device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (!coupled_coherence)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) smp_mb__before_atomic();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) atomic_inc(a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) while (atomic_read(a) < online)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (atomic_inc_return(a) == online * 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) atomic_set(a, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) while (atomic_read(a) > online)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int cps_pm_enter_state(enum cps_pm_state state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned core = cpu_core(¤t_cpu_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned online, left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) cpumask_t *coupled_mask = this_cpu_ptr(&online_coupled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 *core_ready_count, *nc_core_ready_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) void *nc_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) cps_nc_entry_fn entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct core_boot_config *core_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct vpe_boot_config *vpe_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Check that there is an entry function for this state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) entry = per_cpu(nc_asm_enter, core)[state];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (!entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Calculate which coupled CPUs (VPEs) are online */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #if defined(CONFIG_MIPS_MT) || defined(CONFIG_CPU_MIPSR6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (cpu_online(cpu)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) cpumask_and(coupled_mask, cpu_online_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) &cpu_sibling_map[cpu]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) online = cpumask_weight(coupled_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) cpumask_clear_cpu(cpu, coupled_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) cpumask_clear(coupled_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) online = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Setup the VPE to run mips_cps_pm_restore when started again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (IS_ENABLED(CONFIG_CPU_PM) && state == CPS_PM_POWER_GATED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Power gating relies upon CPS SMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (!mips_cps_smp_in_use())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) core_cfg = &mips_cps_core_bootcfg[core];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) vpe_cfg = &core_cfg->vpe_config[cpu_vpe_id(¤t_cpu_data)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) vpe_cfg->pc = (unsigned long)mips_cps_pm_restore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) vpe_cfg->gp = (unsigned long)current_thread_info();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) vpe_cfg->sp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Indicate that this CPU might not be coherent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) cpumask_clear_cpu(cpu, &cpu_coherent_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) smp_mb__after_atomic();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Create a non-coherent mapping of the core ready_count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) core_ready_count = per_cpu(ready_count, core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) nc_addr = kmap_noncoherent(virt_to_page(core_ready_count),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) (unsigned long)core_ready_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) nc_addr += ((unsigned long)core_ready_count & ~PAGE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) nc_core_ready_count = nc_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Ensure ready_count is zero-initialised before the assembly runs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) WRITE_ONCE(*nc_core_ready_count, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) coupled_barrier(&per_cpu(pm_barrier, core), online);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Run the generated entry code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) left = entry(online, nc_core_ready_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Remove the non-coherent mapping of ready_count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) kunmap_noncoherent();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Indicate that this CPU is definitely coherent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) cpumask_set_cpu(cpu, &cpu_coherent_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * If this VPE is the first to leave the non-coherent wait state then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * it needs to wake up any coupled VPEs still running their wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * instruction so that they return to cpuidle, which can then complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * coordination between the coupled VPEs & provide the governor with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * a chance to reflect on the length of time the VPEs were in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * idle state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (coupled_coherence && (state == CPS_PM_NC_WAIT) && (left == online))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) arch_send_call_function_ipi_mask(coupled_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void cps_gen_cache_routine(u32 **pp, struct uasm_label **pl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct uasm_reloc **pr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) const struct cache_desc *cache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned op, int lbl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned cache_size = cache->ways << cache->waybit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) const unsigned unroll_lines = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* If the cache isn't present this function has it easy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (cache->flags & MIPS_CACHE_NOT_PRESENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Load base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) UASM_i_LA(pp, t0, (long)CKSEG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Calculate end address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (cache_size < 0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) uasm_i_addiu(pp, t1, t0, cache_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) UASM_i_LA(pp, t1, (long)(CKSEG0 + cache_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* Start of cache op loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) uasm_build_label(pl, *pp, lbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Generate the cache ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) for (i = 0; i < unroll_lines; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (cpu_has_mips_r6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) uasm_i_cache(pp, op, 0, t0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) uasm_i_addiu(pp, t0, t0, cache->linesz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) uasm_i_cache(pp, op, i * cache->linesz, t0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (!cpu_has_mips_r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Update the base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) uasm_i_addiu(pp, t0, t0, unroll_lines * cache->linesz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Loop if we haven't reached the end address yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) uasm_il_bne(pp, pr, t0, t1, lbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) uasm_i_nop(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int cps_gen_flush_fsb(u32 **pp, struct uasm_label **pl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct uasm_reloc **pr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) const struct cpuinfo_mips *cpu_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int lbl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned i, fsb_size = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned num_loads = (fsb_size * 3) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned line_stride = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned line_size = cpu_info->dcache.linesz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned perf_counter, perf_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) unsigned revision = cpu_info->processor_id & PRID_REV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * Determine whether this CPU requires an FSB flush, and if so which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * performance counter/event reflect stalls due to a full FSB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) switch (__get_cpu_type(cpu_info->cputype)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) case CPU_INTERAPTIV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) perf_counter = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) perf_event = 51;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case CPU_PROAPTIV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Newer proAptiv cores don't require this workaround */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (revision >= PRID_REV_ENCODE_332(1, 1, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* On older ones it's unavailable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* Assume that the CPU does not need this workaround */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * Ensure that the fill/store buffer (FSB) is not holding the results
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * of a prefetch, since if it is then the CPC sequencer may become
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * stuck in the D3 (ClrBus) state whilst entering a low power state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* Preserve perf counter setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) uasm_i_mfc0(pp, t2, 25, (perf_counter * 2) + 0); /* PerfCtlN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) uasm_i_mfc0(pp, t3, 25, (perf_counter * 2) + 1); /* PerfCntN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Setup perf counter to count FSB full pipeline stalls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) uasm_i_addiu(pp, t0, zero, (perf_event << 5) | 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) uasm_i_mtc0(pp, t0, 25, (perf_counter * 2) + 0); /* PerfCtlN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) uasm_i_ehb(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) uasm_i_mtc0(pp, zero, 25, (perf_counter * 2) + 1); /* PerfCntN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) uasm_i_ehb(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Base address for loads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) UASM_i_LA(pp, t0, (long)CKSEG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* Start of clear loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) uasm_build_label(pl, *pp, lbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* Perform some loads to fill the FSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) for (i = 0; i < num_loads; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) uasm_i_lw(pp, zero, i * line_size * line_stride, t0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * Invalidate the new D-cache entries so that the cache will need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * refilling (via the FSB) if the loop is executed again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) for (i = 0; i < num_loads; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) uasm_i_cache(pp, Hit_Invalidate_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) i * line_size * line_stride, t0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) uasm_i_cache(pp, Hit_Writeback_Inv_SD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) i * line_size * line_stride, t0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* Barrier ensuring previous cache invalidates are complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) uasm_i_sync(pp, __SYNC_full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) uasm_i_ehb(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* Check whether the pipeline stalled due to the FSB being full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) uasm_i_mfc0(pp, t1, 25, (perf_counter * 2) + 1); /* PerfCntN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* Loop if it didn't */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) uasm_il_beqz(pp, pr, t1, lbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) uasm_i_nop(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Restore perf counter 1. The count may well now be wrong... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) uasm_i_mtc0(pp, t2, 25, (perf_counter * 2) + 0); /* PerfCtlN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) uasm_i_ehb(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) uasm_i_mtc0(pp, t3, 25, (perf_counter * 2) + 1); /* PerfCntN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) uasm_i_ehb(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static void cps_gen_set_top_bit(u32 **pp, struct uasm_label **pl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct uasm_reloc **pr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned r_addr, int lbl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) uasm_i_lui(pp, t0, uasm_rel_hi(0x80000000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) uasm_build_label(pl, *pp, lbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) uasm_i_ll(pp, t1, 0, r_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) uasm_i_or(pp, t1, t1, t0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) uasm_i_sc(pp, t1, 0, r_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) uasm_il_beqz(pp, pr, t1, lbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) uasm_i_nop(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static void *cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct uasm_label *l = labels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct uasm_reloc *r = relocs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u32 *buf, *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) const unsigned r_online = a0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) const unsigned r_nc_count = a1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) const unsigned r_pcohctl = t7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) const unsigned max_instrs = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) unsigned cpc_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) lbl_incready = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) lbl_poll_cont,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) lbl_secondary_hang,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) lbl_disable_coherence,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) lbl_flush_fsb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) lbl_invicache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) lbl_flushdcache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) lbl_hang,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) lbl_set_cont,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) lbl_secondary_cont,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) lbl_decready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* Allocate a buffer to hold the generated code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) p = buf = kcalloc(max_instrs, sizeof(u32), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (!buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* Clear labels & relocs ready for (re)use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) memset(labels, 0, sizeof(labels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) memset(relocs, 0, sizeof(relocs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (IS_ENABLED(CONFIG_CPU_PM) && state == CPS_PM_POWER_GATED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Power gating relies upon CPS SMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (!mips_cps_smp_in_use())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * Save CPU state. Note the non-standard calling convention
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * with the return address placed in v0 to avoid clobbering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * the ra register before it is saved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) UASM_i_LA(&p, t0, (long)mips_cps_pm_save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) uasm_i_jalr(&p, v0, t0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) uasm_i_nop(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * Load addresses of required CM & CPC registers. This is done early
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * because they're needed in both the enable & disable coherence steps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * but in the coupled case the enable step will only run on one VPE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) UASM_i_LA(&p, r_pcohctl, (long)addr_gcr_cl_coherence());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (coupled_coherence) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* Increment ready_count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) uasm_i_sync(&p, __SYNC_mb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) uasm_build_label(&l, p, lbl_incready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) uasm_i_ll(&p, t1, 0, r_nc_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) uasm_i_addiu(&p, t2, t1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) uasm_i_sc(&p, t2, 0, r_nc_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) uasm_il_beqz(&p, &r, t2, lbl_incready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) uasm_i_addiu(&p, t1, t1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* Barrier ensuring all CPUs see the updated r_nc_count value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) uasm_i_sync(&p, __SYNC_mb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * If this is the last VPE to become ready for non-coherence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * then it should branch below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) uasm_il_beq(&p, &r, t1, r_online, lbl_disable_coherence);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) uasm_i_nop(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (state < CPS_PM_POWER_GATED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * Otherwise this is not the last VPE to become ready
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * for non-coherence. It needs to wait until coherence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * has been disabled before proceeding, which it will do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * by polling for the top bit of ready_count being set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) uasm_i_addiu(&p, t1, zero, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) uasm_build_label(&l, p, lbl_poll_cont);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) uasm_i_lw(&p, t0, 0, r_nc_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) uasm_il_bltz(&p, &r, t0, lbl_secondary_cont);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) uasm_i_ehb(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (cpu_has_mipsmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) uasm_i_yield(&p, zero, t1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) uasm_il_b(&p, &r, lbl_poll_cont);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) uasm_i_nop(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * The core will lose power & this VPE will not continue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * so it can simply halt here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (cpu_has_mipsmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* Halt the VPE via C0 tchalt register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) uasm_i_addiu(&p, t0, zero, TCHALT_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) uasm_i_mtc0(&p, t0, 2, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) } else if (cpu_has_vp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* Halt the VP via the CPC VP_STOP register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) unsigned int vpe_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) vpe_id = cpu_vpe_id(&cpu_data[cpu]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) uasm_i_addiu(&p, t0, zero, 1 << vpe_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) UASM_i_LA(&p, t1, (long)addr_cpc_cl_vp_stop());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) uasm_i_sw(&p, t0, 0, t1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) uasm_build_label(&l, p, lbl_secondary_hang);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) uasm_il_b(&p, &r, lbl_secondary_hang);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) uasm_i_nop(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * This is the point of no return - this VPE will now proceed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * disable coherence. At this point we *must* be sure that no other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * VPE within the core will interfere with the L1 dcache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) uasm_build_label(&l, p, lbl_disable_coherence);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* Invalidate the L1 icache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) cps_gen_cache_routine(&p, &l, &r, &cpu_data[cpu].icache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) Index_Invalidate_I, lbl_invicache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* Writeback & invalidate the L1 dcache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) cps_gen_cache_routine(&p, &l, &r, &cpu_data[cpu].dcache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) Index_Writeback_Inv_D, lbl_flushdcache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* Barrier ensuring previous cache invalidates are complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) uasm_i_sync(&p, __SYNC_full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) uasm_i_ehb(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (mips_cm_revision() < CM_REV_CM3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * Disable all but self interventions. The load from COHCTL is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * defined by the interAptiv & proAptiv SUMs as ensuring that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * operation resulting from the preceding store is complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) uasm_i_addiu(&p, t0, zero, 1 << cpu_core(&cpu_data[cpu]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) uasm_i_sw(&p, t0, 0, r_pcohctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) uasm_i_lw(&p, t0, 0, r_pcohctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* Barrier to ensure write to coherence control is complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) uasm_i_sync(&p, __SYNC_full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) uasm_i_ehb(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* Disable coherence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) uasm_i_sw(&p, zero, 0, r_pcohctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) uasm_i_lw(&p, t0, 0, r_pcohctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (state >= CPS_PM_CLOCK_GATED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) err = cps_gen_flush_fsb(&p, &l, &r, &cpu_data[cpu],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) lbl_flush_fsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* Determine the CPC command to issue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) case CPS_PM_CLOCK_GATED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) cpc_cmd = CPC_Cx_CMD_CLOCKOFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) case CPS_PM_POWER_GATED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) cpc_cmd = CPC_Cx_CMD_PWRDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* Issue the CPC command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) UASM_i_LA(&p, t0, (long)addr_cpc_cl_cmd());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) uasm_i_addiu(&p, t1, zero, cpc_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) uasm_i_sw(&p, t1, 0, t0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (state == CPS_PM_POWER_GATED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* If anything goes wrong just hang */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) uasm_build_label(&l, p, lbl_hang);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) uasm_il_b(&p, &r, lbl_hang);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) uasm_i_nop(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * There's no point generating more code, the core is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * powered down & if powered back up will run from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * reset vector not from here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) goto gen_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* Barrier to ensure write to CPC command is complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) uasm_i_sync(&p, __SYNC_full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) uasm_i_ehb(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (state == CPS_PM_NC_WAIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * At this point it is safe for all VPEs to proceed with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * execution. This VPE will set the top bit of ready_count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * to indicate to the other VPEs that they may continue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (coupled_coherence)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) cps_gen_set_top_bit(&p, &l, &r, r_nc_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) lbl_set_cont);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * VPEs which did not disable coherence will continue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * executing, after coherence has been disabled, from this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) uasm_build_label(&l, p, lbl_secondary_cont);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* Now perform our wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) uasm_i_wait(&p, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * Re-enable coherence. Note that for CPS_PM_NC_WAIT all coupled VPEs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * will run this. The first will actually re-enable coherence & the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * rest will just be performing a rather unusual nop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) uasm_i_addiu(&p, t0, zero, mips_cm_revision() < CM_REV_CM3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ? CM_GCR_Cx_COHERENCE_COHDOMAINEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) : CM3_GCR_Cx_COHERENCE_COHEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) uasm_i_sw(&p, t0, 0, r_pcohctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) uasm_i_lw(&p, t0, 0, r_pcohctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* Barrier to ensure write to coherence control is complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) uasm_i_sync(&p, __SYNC_full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) uasm_i_ehb(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (coupled_coherence && (state == CPS_PM_NC_WAIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* Decrement ready_count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) uasm_build_label(&l, p, lbl_decready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) uasm_i_sync(&p, __SYNC_mb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) uasm_i_ll(&p, t1, 0, r_nc_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) uasm_i_addiu(&p, t2, t1, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) uasm_i_sc(&p, t2, 0, r_nc_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) uasm_il_beqz(&p, &r, t2, lbl_decready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) uasm_i_andi(&p, v0, t1, (1 << fls(smp_num_siblings)) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* Barrier ensuring all CPUs see the updated r_nc_count value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) uasm_i_sync(&p, __SYNC_mb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (coupled_coherence && (state == CPS_PM_CLOCK_GATED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * At this point it is safe for all VPEs to proceed with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * execution. This VPE will set the top bit of ready_count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * to indicate to the other VPEs that they may continue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) cps_gen_set_top_bit(&p, &l, &r, r_nc_count, lbl_set_cont);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * This core will be reliant upon another core sending a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * power-up command to the CPC in order to resume operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * Thus an arbitrary VPE can't trigger the core leaving the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * idle state and the one that disables coherence might as well
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * be the one to re-enable it. The rest will continue from here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * after that has been done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) uasm_build_label(&l, p, lbl_secondary_cont);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* Barrier ensuring all CPUs see the updated r_nc_count value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) uasm_i_sync(&p, __SYNC_mb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* The core is coherent, time to return to C code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) uasm_i_jr(&p, ra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) uasm_i_nop(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) gen_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* Ensure the code didn't exceed the resources allocated for it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) BUG_ON((p - buf) > max_instrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) BUG_ON((l - labels) > ARRAY_SIZE(labels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) BUG_ON((r - relocs) > ARRAY_SIZE(relocs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* Patch branch offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) uasm_resolve_relocs(relocs, labels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* Flush the icache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) local_flush_icache_range((unsigned long)buf, (unsigned long)p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static int cps_pm_online_cpu(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) enum cps_pm_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) unsigned core = cpu_core(&cpu_data[cpu]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) void *entry_fn, *core_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) for (state = CPS_PM_NC_WAIT; state < CPS_PM_STATE_COUNT; state++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (per_cpu(nc_asm_enter, core)[state])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (!test_bit(state, state_support))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) entry_fn = cps_gen_entry_code(cpu, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (!entry_fn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) pr_err("Failed to generate core %u state %u entry\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) core, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) clear_bit(state, state_support);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) per_cpu(nc_asm_enter, core)[state] = entry_fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (!per_cpu(ready_count, core)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) core_rc = kmalloc(sizeof(u32), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (!core_rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) pr_err("Failed allocate core %u ready_count\n", core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) per_cpu(ready_count, core) = core_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static int cps_pm_power_notifier(struct notifier_block *this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) unsigned long event, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) unsigned int stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) switch (event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) case PM_SUSPEND_PREPARE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) stat = read_cpc_cl_stat_conf();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * If we're attempting to suspend the system and power down all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * of the cores, the JTAG detect bit indicates that the CPC will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * instead put the cores into clock-off state. In this state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * a connected debugger can cause the CPU to attempt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * interactions with the powered down system. At best this will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * fail. At worst, it can hang the NoC, requiring a hard reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * To avoid this, just block system suspend if a JTAG probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * is detected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (stat & CPC_Cx_STAT_CONF_EJTAG_PROBE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) pr_warn("JTAG probe is connected - abort suspend\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return NOTIFY_BAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static int __init cps_pm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /* A CM is required for all non-coherent states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (!mips_cm_present()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) pr_warn("pm-cps: no CM, non-coherent states unavailable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * If interrupts were enabled whilst running a wait instruction on a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * non-coherent core then the VPE may end up processing interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * whilst non-coherent. That would be bad.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (cpu_wait == r4k_wait_irqoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) set_bit(CPS_PM_NC_WAIT, state_support);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) pr_warn("pm-cps: non-coherent wait unavailable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* Detect whether a CPC is present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (mips_cpc_present()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* Detect whether clock gating is implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (read_cpc_cl_stat_conf() & CPC_Cx_STAT_CONF_CLKGAT_IMPL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) set_bit(CPS_PM_CLOCK_GATED, state_support);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) pr_warn("pm-cps: CPC does not support clock gating\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /* Power gating is available with CPS SMP & any CPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (mips_cps_smp_in_use())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) set_bit(CPS_PM_POWER_GATED, state_support);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) pr_warn("pm-cps: CPS SMP not in use, power gating unavailable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) pr_warn("pm-cps: no CPC, clock & power gating unavailable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) pm_notifier(cps_pm_power_notifier, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "mips/cps_pm:online",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) cps_pm_online_cpu, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) arch_initcall(cps_pm_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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