^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 1994, 1995, 1996, by Andreas Busse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 1999 Silicon Graphics, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2000 MIPS Technologies, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * written by Carsten Langgaard, carstenl@mips.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/regdef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/stackframe.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * task_struct *resume(task_struct *prev, task_struct *next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * struct thread_info *next_ti)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .align 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) LEAF(resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .set arch=octeon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) mfc0 t1, CP0_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) LONG_S t1, THREAD_STATUS(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) cpu_save_nonscratch a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) LONG_S ra, THREAD_REG31(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Check if we need to store CVMSEG state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) dmfc0 t0, $11,7 /* CvmMemCtl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) bbit0 t0, 6, 3f /* Is user access enabled? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Store the CVMSEG state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Extract the size of CVMSEG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) andi t0, 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Multiply * (cache line size/sizeof(long)/2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) sll t0, 7-LONGLOG-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) li t1, -32768 /* Base address of CVMSEG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) LONG_ADDI t2, a0, THREAD_CVMSEG /* Where to store CVMSEG to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) synciobdma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .set noreorder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) LONG_L t8, 0(t1) /* Load from CVMSEG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) subu t0, 1 /* Decrement loop var */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) LONG_L t9, LONGSIZE(t1)/* Load from CVMSEG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) LONG_ADDU t1, LONGSIZE*2 /* Increment loc in CVMSEG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) LONG_S t8, 0(t2) /* Store CVMSEG to thread storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) LONG_ADDU t2, LONGSIZE*2 /* Increment loc in thread storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) bnez t0, 2b /* Loop until we've copied it all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) LONG_S t9, -LONGSIZE(t2)/* Store CVMSEG to thread storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .set reorder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Disable access to CVMSEG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) dmfc0 t0, $11,7 /* CvmMemCtl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) xori t0, t0, 0x40 /* Bit 6 is CVMSEG user enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) dmtc0 t0, $11,7 /* CvmMemCtl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PTR_LA t8, __stack_chk_guard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) LONG_L t9, TASK_STACK_CANARY(a1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) LONG_S t9, 0(t8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * The order of restoring the registers takes care of the race
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * updating $28, $29 and kernelsp without disabling ints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) move $28, a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) cpu_restore_nonscratch a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) PTR_ADDU t0, $28, _THREAD_SIZE - 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) set_saved_sp t0, t1, t2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) mfc0 t1, CP0_STATUS /* Do we really need this? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) li a3, 0xff01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) and t1, a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) LONG_L a2, THREAD_STATUS(a1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) nor a3, $0, a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) and a2, a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) or a2, t1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) mtc0 a2, CP0_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) move v0, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) jr ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) END(resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * void octeon_cop2_save(struct octeon_cop2_state *a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .align 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .set push
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .set noreorder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) LEAF(octeon_cop2_save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) dmfc0 t9, $9,7 /* CvmCtl register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Save the COP2 CRC state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) dmfc2 t0, 0x0201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) dmfc2 t1, 0x0202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) dmfc2 t2, 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) sd t0, OCTEON_CP2_CRC_IV(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) sd t1, OCTEON_CP2_CRC_LENGTH(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Skip next instructions if CvmCtl[NODFA_CP2] set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) bbit1 t9, 28, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) sd t2, OCTEON_CP2_CRC_POLY(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Save the LLM state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) dmfc2 t0, 0x0402
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) dmfc2 t1, 0x040A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) sd t0, OCTEON_CP2_LLM_DAT(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 1: bbit1 t9, 26, 3f /* done if CvmCtl[NOCRYPTO] set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) sd t1, OCTEON_CP2_LLM_DAT+8(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Save the COP2 crypto state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* this part is mostly common to both pass 1 and later revisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) dmfc2 t0, 0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dmfc2 t1, 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) dmfc2 t2, 0x0081
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) dmfc2 t3, 0x0082
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) sd t0, OCTEON_CP2_3DES_IV(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) dmfc2 t0, 0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) sd t1, OCTEON_CP2_3DES_KEY(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) dmfc2 t1, 0x0111 /* only necessary for pass 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) sd t2, OCTEON_CP2_3DES_KEY+8(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) dmfc2 t2, 0x0102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) sd t3, OCTEON_CP2_3DES_KEY+16(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) dmfc2 t3, 0x0103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) sd t0, OCTEON_CP2_3DES_RESULT(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) dmfc2 t0, 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) sd t1, OCTEON_CP2_AES_INP0(a0) /* only necessary for pass 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) dmfc2 t1, 0x0105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) sd t2, OCTEON_CP2_AES_IV(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) dmfc2 t2, 0x0106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) sd t3, OCTEON_CP2_AES_IV+8(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dmfc2 t3, 0x0107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) sd t0, OCTEON_CP2_AES_KEY(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) dmfc2 t0, 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) sd t1, OCTEON_CP2_AES_KEY+8(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) dmfc2 t1, 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) sd t2, OCTEON_CP2_AES_KEY+16(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dmfc2 t2, 0x0101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) sd t3, OCTEON_CP2_AES_KEY+24(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) mfc0 v0, $15,0 /* Get the processor ID register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) sd t0, OCTEON_CP2_AES_KEYLEN(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) li v1, 0x000d0000 /* This is the processor ID of Octeon Pass1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) sd t1, OCTEON_CP2_AES_RESULT(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Skip to the Pass1 version of the remainder of the COP2 state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) beq v0, v1, 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) sd t2, OCTEON_CP2_AES_RESULT+8(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* the non-pass1 state when !CvmCtl[NOCRYPTO] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) dmfc2 t1, 0x0240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) dmfc2 t2, 0x0241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ori v1, v1, 0x9500 /* lowest OCTEON III PrId*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dmfc2 t3, 0x0242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) subu v1, v0, v1 /* prid - lowest OCTEON III PrId */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dmfc2 t0, 0x0243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) sd t1, OCTEON_CP2_HSH_DATW(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) dmfc2 t1, 0x0244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) sd t2, OCTEON_CP2_HSH_DATW+8(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dmfc2 t2, 0x0245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) sd t3, OCTEON_CP2_HSH_DATW+16(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) dmfc2 t3, 0x0246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) sd t0, OCTEON_CP2_HSH_DATW+24(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) dmfc2 t0, 0x0247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) sd t1, OCTEON_CP2_HSH_DATW+32(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) dmfc2 t1, 0x0248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) sd t2, OCTEON_CP2_HSH_DATW+40(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dmfc2 t2, 0x0249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) sd t3, OCTEON_CP2_HSH_DATW+48(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) dmfc2 t3, 0x024A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) sd t0, OCTEON_CP2_HSH_DATW+56(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) dmfc2 t0, 0x024B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) sd t1, OCTEON_CP2_HSH_DATW+64(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) dmfc2 t1, 0x024C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) sd t2, OCTEON_CP2_HSH_DATW+72(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dmfc2 t2, 0x024D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) sd t3, OCTEON_CP2_HSH_DATW+80(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) dmfc2 t3, 0x024E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) sd t0, OCTEON_CP2_HSH_DATW+88(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dmfc2 t0, 0x0250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) sd t1, OCTEON_CP2_HSH_DATW+96(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dmfc2 t1, 0x0251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) sd t2, OCTEON_CP2_HSH_DATW+104(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dmfc2 t2, 0x0252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) sd t3, OCTEON_CP2_HSH_DATW+112(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) dmfc2 t3, 0x0253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) sd t0, OCTEON_CP2_HSH_IVW(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) dmfc2 t0, 0x0254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) sd t1, OCTEON_CP2_HSH_IVW+8(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) dmfc2 t1, 0x0255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) sd t2, OCTEON_CP2_HSH_IVW+16(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dmfc2 t2, 0x0256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) sd t3, OCTEON_CP2_HSH_IVW+24(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dmfc2 t3, 0x0257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) sd t0, OCTEON_CP2_HSH_IVW+32(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) dmfc2 t0, 0x0258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) sd t1, OCTEON_CP2_HSH_IVW+40(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dmfc2 t1, 0x0259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) sd t2, OCTEON_CP2_HSH_IVW+48(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dmfc2 t2, 0x025E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) sd t3, OCTEON_CP2_HSH_IVW+56(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) dmfc2 t3, 0x025A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) sd t0, OCTEON_CP2_GFM_MULT(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) dmfc2 t0, 0x025B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) sd t1, OCTEON_CP2_GFM_MULT+8(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) sd t2, OCTEON_CP2_GFM_POLY(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) sd t3, OCTEON_CP2_GFM_RESULT(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) bltz v1, 4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) sd t0, OCTEON_CP2_GFM_RESULT+8(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* OCTEON III things*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) dmfc2 t0, 0x024F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) dmfc2 t1, 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) sd t0, OCTEON_CP2_SHA3(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) sd t1, OCTEON_CP2_SHA3+8(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) jr ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 2: /* pass 1 special stuff when !CvmCtl[NOCRYPTO] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) dmfc2 t3, 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dmfc2 t0, 0x0041
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dmfc2 t1, 0x0042
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dmfc2 t2, 0x0043
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) sd t3, OCTEON_CP2_HSH_DATW(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dmfc2 t3, 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) sd t0, OCTEON_CP2_HSH_DATW+8(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) dmfc2 t0, 0x0045
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) sd t1, OCTEON_CP2_HSH_DATW+16(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) dmfc2 t1, 0x0046
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) sd t2, OCTEON_CP2_HSH_DATW+24(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dmfc2 t2, 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) sd t3, OCTEON_CP2_HSH_DATW+32(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dmfc2 t3, 0x0049
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) sd t0, OCTEON_CP2_HSH_DATW+40(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dmfc2 t0, 0x004A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) sd t1, OCTEON_CP2_HSH_DATW+48(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) sd t2, OCTEON_CP2_HSH_IVW(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) sd t3, OCTEON_CP2_HSH_IVW+8(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) sd t0, OCTEON_CP2_HSH_IVW+16(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 3: /* pass 1 or CvmCtl[NOCRYPTO] set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) jr ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) END(octeon_cop2_save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .set pop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * void octeon_cop2_restore(struct octeon_cop2_state *a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .align 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .set push
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .set noreorder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) LEAF(octeon_cop2_restore)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* First cache line was prefetched before the call */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) pref 4, 128(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) dmfc0 t9, $9,7 /* CvmCtl register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) pref 4, 256(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ld t0, OCTEON_CP2_CRC_IV(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) pref 4, 384(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ld t1, OCTEON_CP2_CRC_LENGTH(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ld t2, OCTEON_CP2_CRC_POLY(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Restore the COP2 CRC state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) dmtc2 t0, 0x0201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) dmtc2 t1, 0x1202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) bbit1 t9, 28, 2f /* Skip LLM if CvmCtl[NODFA_CP2] is set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dmtc2 t2, 0x4200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* Restore the LLM state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ld t0, OCTEON_CP2_LLM_DAT(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ld t1, OCTEON_CP2_LLM_DAT+8(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dmtc2 t0, 0x0402
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dmtc2 t1, 0x040A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) bbit1 t9, 26, done_restore /* done if CvmCtl[NOCRYPTO] set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Restore the COP2 crypto state common to pass 1 and pass 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ld t0, OCTEON_CP2_3DES_IV(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ld t1, OCTEON_CP2_3DES_KEY(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ld t2, OCTEON_CP2_3DES_KEY+8(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) dmtc2 t0, 0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ld t0, OCTEON_CP2_3DES_KEY+16(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dmtc2 t1, 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ld t1, OCTEON_CP2_3DES_RESULT(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dmtc2 t2, 0x0081
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ld t2, OCTEON_CP2_AES_INP0(a0) /* only really needed for pass 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dmtc2 t0, 0x0082
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ld t0, OCTEON_CP2_AES_IV(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) dmtc2 t1, 0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ld t1, OCTEON_CP2_AES_IV+8(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) dmtc2 t2, 0x010A /* only really needed for pass 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ld t2, OCTEON_CP2_AES_KEY(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) dmtc2 t0, 0x0102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ld t0, OCTEON_CP2_AES_KEY+8(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) dmtc2 t1, 0x0103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ld t1, OCTEON_CP2_AES_KEY+16(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) dmtc2 t2, 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ld t2, OCTEON_CP2_AES_KEY+24(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dmtc2 t0, 0x0105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ld t0, OCTEON_CP2_AES_KEYLEN(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) dmtc2 t1, 0x0106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ld t1, OCTEON_CP2_AES_RESULT(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dmtc2 t2, 0x0107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ld t2, OCTEON_CP2_AES_RESULT+8(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) mfc0 t3, $15,0 /* Get the processor ID register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dmtc2 t0, 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) li v0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) dmtc2 t1, 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) bne v0, t3, 3f /* Skip the next stuff for non-pass1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dmtc2 t2, 0x0101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* this code is specific for pass 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ld t0, OCTEON_CP2_HSH_DATW(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ld t1, OCTEON_CP2_HSH_DATW+8(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ld t2, OCTEON_CP2_HSH_DATW+16(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) dmtc2 t0, 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ld t0, OCTEON_CP2_HSH_DATW+24(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) dmtc2 t1, 0x0041
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ld t1, OCTEON_CP2_HSH_DATW+32(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) dmtc2 t2, 0x0042
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ld t2, OCTEON_CP2_HSH_DATW+40(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) dmtc2 t0, 0x0043
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ld t0, OCTEON_CP2_HSH_DATW+48(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dmtc2 t1, 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ld t1, OCTEON_CP2_HSH_IVW(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) dmtc2 t2, 0x0045
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ld t2, OCTEON_CP2_HSH_IVW+8(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) dmtc2 t0, 0x0046
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ld t0, OCTEON_CP2_HSH_IVW+16(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dmtc2 t1, 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) dmtc2 t2, 0x0049
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) b done_restore /* unconditional branch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dmtc2 t0, 0x004A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 3: /* this is post-pass1 code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ld t2, OCTEON_CP2_HSH_DATW(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ori v0, v0, 0x9500 /* lowest OCTEON III PrId*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ld t0, OCTEON_CP2_HSH_DATW+8(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ld t1, OCTEON_CP2_HSH_DATW+16(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dmtc2 t2, 0x0240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ld t2, OCTEON_CP2_HSH_DATW+24(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dmtc2 t0, 0x0241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ld t0, OCTEON_CP2_HSH_DATW+32(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) dmtc2 t1, 0x0242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ld t1, OCTEON_CP2_HSH_DATW+40(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) dmtc2 t2, 0x0243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ld t2, OCTEON_CP2_HSH_DATW+48(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) dmtc2 t0, 0x0244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ld t0, OCTEON_CP2_HSH_DATW+56(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) dmtc2 t1, 0x0245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ld t1, OCTEON_CP2_HSH_DATW+64(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) dmtc2 t2, 0x0246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ld t2, OCTEON_CP2_HSH_DATW+72(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) dmtc2 t0, 0x0247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ld t0, OCTEON_CP2_HSH_DATW+80(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) dmtc2 t1, 0x0248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ld t1, OCTEON_CP2_HSH_DATW+88(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dmtc2 t2, 0x0249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ld t2, OCTEON_CP2_HSH_DATW+96(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) dmtc2 t0, 0x024A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ld t0, OCTEON_CP2_HSH_DATW+104(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dmtc2 t1, 0x024B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ld t1, OCTEON_CP2_HSH_DATW+112(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dmtc2 t2, 0x024C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ld t2, OCTEON_CP2_HSH_IVW(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) dmtc2 t0, 0x024D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ld t0, OCTEON_CP2_HSH_IVW+8(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dmtc2 t1, 0x024E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ld t1, OCTEON_CP2_HSH_IVW+16(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dmtc2 t2, 0x0250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ld t2, OCTEON_CP2_HSH_IVW+24(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dmtc2 t0, 0x0251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ld t0, OCTEON_CP2_HSH_IVW+32(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) dmtc2 t1, 0x0252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ld t1, OCTEON_CP2_HSH_IVW+40(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) dmtc2 t2, 0x0253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ld t2, OCTEON_CP2_HSH_IVW+48(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) dmtc2 t0, 0x0254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ld t0, OCTEON_CP2_HSH_IVW+56(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dmtc2 t1, 0x0255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ld t1, OCTEON_CP2_GFM_MULT(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dmtc2 t2, 0x0256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ld t2, OCTEON_CP2_GFM_MULT+8(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dmtc2 t0, 0x0257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ld t0, OCTEON_CP2_GFM_POLY(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dmtc2 t1, 0x0258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ld t1, OCTEON_CP2_GFM_RESULT(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dmtc2 t2, 0x0259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ld t2, OCTEON_CP2_GFM_RESULT+8(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) dmtc2 t0, 0x025E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) subu v0, t3, v0 /* prid - lowest OCTEON III PrId */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) dmtc2 t1, 0x025A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) bltz v0, done_restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) dmtc2 t2, 0x025B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* OCTEON III things*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ld t0, OCTEON_CP2_SHA3(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ld t1, OCTEON_CP2_SHA3+8(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dmtc2 t0, 0x0051
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dmtc2 t1, 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) done_restore:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) jr ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) END(octeon_cop2_restore)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .set pop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * void octeon_mult_save()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * sp is assumed to point to a struct pt_regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * NOTE: This is called in SAVE_TEMP in stackframe.h. It can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * safely modify v1,k0, k1,$10-$15, and $24. It will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * be overwritten with a processor specific version of the code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .p2align 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .set push
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .set noreorder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) LEAF(octeon_mult_save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) jr ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .space 30 * 4, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) octeon_mult_save_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) EXPORT(octeon_mult_save_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) END(octeon_mult_save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) LEAF(octeon_mult_save2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* Save the multiplier state OCTEON II and earlier*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) v3mulu k0, $0, $0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) v3mulu k1, $0, $0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) sd k0, PT_MTP(sp) /* PT_MTP has P0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) v3mulu k0, $0, $0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) sd k1, PT_MTP+8(sp) /* PT_MTP+8 has P1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ori k1, $0, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) v3mulu k1, k1, $0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) sd k0, PT_MTP+16(sp) /* PT_MTP+16 has P2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) v3mulu k0, $0, $0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) sd k1, PT_MPL(sp) /* PT_MPL has MPL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) v3mulu k1, $0, $0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) sd k0, PT_MPL+8(sp) /* PT_MPL+8 has MPL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) jr ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) sd k1, PT_MPL+16(sp) /* PT_MPL+16 has MPL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) octeon_mult_save2_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) EXPORT(octeon_mult_save2_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) END(octeon_mult_save2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) LEAF(octeon_mult_save3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* Save the multiplier state OCTEON III */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) v3mulu $10, $0, $0 /* read P0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) v3mulu $11, $0, $0 /* read P1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) v3mulu $12, $0, $0 /* read P2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) sd $10, PT_MTP+(0*8)(sp) /* store P0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) v3mulu $10, $0, $0 /* read P3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) sd $11, PT_MTP+(1*8)(sp) /* store P1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) v3mulu $11, $0, $0 /* read P4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) sd $12, PT_MTP+(2*8)(sp) /* store P2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ori $13, $0, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) v3mulu $12, $0, $0 /* read P5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) sd $10, PT_MTP+(3*8)(sp) /* store P3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) v3mulu $13, $13, $0 /* P4-P0 = MPL5-MPL1, $13 = MPL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) sd $11, PT_MTP+(4*8)(sp) /* store P4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) v3mulu $10, $0, $0 /* read MPL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) sd $12, PT_MTP+(5*8)(sp) /* store P5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) v3mulu $11, $0, $0 /* read MPL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) sd $13, PT_MPL+(0*8)(sp) /* store MPL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) v3mulu $12, $0, $0 /* read MPL3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) sd $10, PT_MPL+(1*8)(sp) /* store MPL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) v3mulu $10, $0, $0 /* read MPL4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) sd $11, PT_MPL+(2*8)(sp) /* store MPL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) v3mulu $11, $0, $0 /* read MPL5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) sd $12, PT_MPL+(3*8)(sp) /* store MPL3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) sd $10, PT_MPL+(4*8)(sp) /* store MPL4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) jr ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) sd $11, PT_MPL+(5*8)(sp) /* store MPL5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) octeon_mult_save3_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) EXPORT(octeon_mult_save3_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) END(octeon_mult_save3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .set pop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * void octeon_mult_restore()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * sp is assumed to point to a struct pt_regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * NOTE: This is called in RESTORE_TEMP in stackframe.h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .p2align 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .set push
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .set noreorder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) LEAF(octeon_mult_restore)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) jr ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .space 30 * 4, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) octeon_mult_restore_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) EXPORT(octeon_mult_restore_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) END(octeon_mult_restore)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) LEAF(octeon_mult_restore2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ld v0, PT_MPL(sp) /* MPL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ld v1, PT_MPL+8(sp) /* MPL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ld k0, PT_MPL+16(sp) /* MPL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* Restore the multiplier state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ld k1, PT_MTP+16(sp) /* P2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) mtm0 v0 /* MPL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) ld v0, PT_MTP+8(sp) /* P1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) mtm1 v1 /* MPL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) ld v1, PT_MTP(sp) /* P0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) mtm2 k0 /* MPL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) mtp2 k1 /* P2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) mtp1 v0 /* P1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) jr ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) mtp0 v1 /* P0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) octeon_mult_restore2_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) EXPORT(octeon_mult_restore2_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) END(octeon_mult_restore2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) LEAF(octeon_mult_restore3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ld $12, PT_MPL+(0*8)(sp) /* read MPL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ld $13, PT_MPL+(3*8)(sp) /* read MPL3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ld $10, PT_MPL+(1*8)(sp) /* read MPL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ld $11, PT_MPL+(4*8)(sp) /* read MPL4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .word 0x718d0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* mtm0 $12, $13 restore MPL0 and MPL3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ld $12, PT_MPL+(2*8)(sp) /* read MPL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .word 0x714b000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* mtm1 $10, $11 restore MPL1 and MPL4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) ld $13, PT_MPL+(5*8)(sp) /* read MPL5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ld $10, PT_MTP+(0*8)(sp) /* read P0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ld $11, PT_MTP+(3*8)(sp) /* read P3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .word 0x718d000d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* mtm2 $12, $13 restore MPL2 and MPL5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ld $12, PT_MTP+(1*8)(sp) /* read P1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .word 0x714b0009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* mtp0 $10, $11 restore P0 and P3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ld $13, PT_MTP+(4*8)(sp) /* read P4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ld $10, PT_MTP+(2*8)(sp) /* read P2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ld $11, PT_MTP+(5*8)(sp) /* read P5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .word 0x718d000a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* mtp1 $12, $13 restore P1 and P4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) jr ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .word 0x714b000b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* mtp2 $10, $11 restore P2 and P5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) octeon_mult_restore3_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) EXPORT(octeon_mult_restore3_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) END(octeon_mult_restore3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .set pop
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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