^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2013 Imagination Technologies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Paul Burton <paul.burton@mips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/percpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/mips-cps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) void __iomem *mips_cpc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static DEFINE_PER_CPU_ALIGNED(spinlock_t, cpc_core_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static DEFINE_PER_CPU_ALIGNED(unsigned long, cpc_core_lock_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) phys_addr_t __weak mips_cpc_default_phys_base(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct device_node *cpc_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) cpc_node = of_find_compatible_node(of_root, NULL, "mti,mips-cpc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) if (cpc_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) err = of_address_to_resource(cpc_node, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) return res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * mips_cpc_phys_base - retrieve the physical base address of the CPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * This function returns the physical base address of the Cluster Power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * Controller memory mapped registers, or 0 if no Cluster Power Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * is present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static phys_addr_t mips_cpc_phys_base(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned long cpc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (!mips_cm_present())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (!(read_gcr_cpc_status() & CM_GCR_CPC_STATUS_EX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* If the CPC is already enabled, leave it so */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) cpc_base = read_gcr_cpc_base();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (cpc_base & CM_GCR_CPC_BASE_CPCEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return cpc_base & CM_GCR_CPC_BASE_CPCBASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Otherwise, use the default address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) cpc_base = mips_cpc_default_phys_base();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (!cpc_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return cpc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Enable the CPC, mapped at the default address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) write_gcr_cpc_base(cpc_base | CM_GCR_CPC_BASE_CPCEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return cpc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int mips_cpc_probe(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) phys_addr_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) for_each_possible_cpu(cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) spin_lock_init(&per_cpu(cpc_core_lock, cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) addr = mips_cpc_phys_base();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (!addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) mips_cpc_base = ioremap(addr, 0x8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (!mips_cpc_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) void mips_cpc_lock_other(unsigned int core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned int curr_core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (mips_cm_revision() >= CM_REV_CM3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Systems with CM >= 3 lock the CPC via mips_cm_lock_other */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) curr_core = cpu_core(¤t_cpu_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) spin_lock_irqsave(&per_cpu(cpc_core_lock, curr_core),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) per_cpu(cpc_core_lock_flags, curr_core));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) write_cpc_cl_other(core << __ffs(CPC_Cx_OTHER_CORENUM));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * Ensure the core-other region reflects the appropriate core &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * VP before any accesses to it occur.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) void mips_cpc_unlock_other(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned int curr_core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (mips_cm_revision() >= CM_REV_CM3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Systems with CM >= 3 lock the CPC via mips_cm_lock_other */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) curr_core = cpu_core(¤t_cpu_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) spin_unlock_irqrestore(&per_cpu(cpc_core_lock, curr_core),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) per_cpu(cpc_core_lock_flags, curr_core));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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