^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2013 Imagination Technologies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Paul Burton <paul.burton@mips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/percpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/mips-cps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) void __iomem *mips_gcr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) void __iomem *mips_cm_l2sync_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) int mips_cm_is64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static char *cm2_tr[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) "mem", "gcr", "gic", "mmio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) "0x04", "cpc", "0x06", "0x07"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* CM3 Tag ECC transaction type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static char *cm3_tr[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) [0x0] = "ReqNoData",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) [0x1] = "0x1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) [0x2] = "ReqWData",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) [0x3] = "0x3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) [0x4] = "IReqNoResp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) [0x5] = "IReqWResp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) [0x6] = "IReqNoRespDat",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) [0x7] = "IReqWRespDat",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) [0x8] = "RespNoData",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) [0x9] = "RespDataFol",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) [0xa] = "RespWData",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) [0xb] = "RespDataOnly",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) [0xc] = "IRespNoData",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) [0xd] = "IRespDataFol",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) [0xe] = "IRespWData",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) [0xf] = "IRespDataOnly"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static char *cm2_cmd[32] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) [0x00] = "0x00",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) [0x01] = "Legacy Write",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) [0x02] = "Legacy Read",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) [0x03] = "0x03",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) [0x04] = "0x04",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) [0x05] = "0x05",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) [0x06] = "0x06",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) [0x07] = "0x07",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) [0x08] = "Coherent Read Own",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) [0x09] = "Coherent Read Share",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) [0x0a] = "Coherent Read Discard",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) [0x0b] = "Coherent Ready Share Always",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) [0x0c] = "Coherent Upgrade",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) [0x0d] = "Coherent Writeback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) [0x0e] = "0x0e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) [0x0f] = "0x0f",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) [0x10] = "Coherent Copyback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) [0x11] = "Coherent Copyback Invalidate",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) [0x12] = "Coherent Invalidate",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) [0x13] = "Coherent Write Invalidate",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) [0x14] = "Coherent Completion Sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) [0x15] = "0x15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) [0x16] = "0x16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) [0x17] = "0x17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) [0x18] = "0x18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) [0x19] = "0x19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) [0x1a] = "0x1a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) [0x1b] = "0x1b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) [0x1c] = "0x1c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) [0x1d] = "0x1d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) [0x1e] = "0x1e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) [0x1f] = "0x1f"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* CM3 Tag ECC command type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static char *cm3_cmd[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) [0x0] = "Legacy Read",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) [0x1] = "Legacy Write",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) [0x2] = "Coherent Read Own",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) [0x3] = "Coherent Read Share",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) [0x4] = "Coherent Read Discard",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) [0x5] = "Coherent Evicted",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) [0x6] = "Coherent Upgrade",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) [0x7] = "Coherent Upgrade for Store Conditional",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) [0x8] = "Coherent Writeback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) [0x9] = "Coherent Write Invalidate",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) [0xa] = "0xa",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) [0xb] = "0xb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) [0xc] = "0xc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) [0xd] = "0xd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) [0xe] = "0xe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) [0xf] = "0xf"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* CM3 Tag ECC command group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static char *cm3_cmd_group[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) [0x0] = "Normal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) [0x1] = "Registers",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) [0x2] = "TLB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) [0x3] = "0x3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) [0x4] = "L1I",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) [0x5] = "L1D",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) [0x6] = "L3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) [0x7] = "L2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static char *cm2_core[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) "Invalid/OK", "Invalid/Data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) "Shared/OK", "Shared/Data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) "Modified/OK", "Modified/Data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) "Exclusive/OK", "Exclusive/Data"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static char *cm2_l2_type[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) [0x0] = "None",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) [0x1] = "Tag RAM single/double ECC error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) [0x2] = "Data RAM single/double ECC error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) [0x3] = "WS RAM uncorrectable dirty parity"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static char *cm2_l2_instr[32] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) [0x00] = "L2_NOP",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) [0x01] = "L2_ERR_CORR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) [0x02] = "L2_TAG_INV",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) [0x03] = "L2_WS_CLEAN",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) [0x04] = "L2_RD_MDYFY_WR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) [0x05] = "L2_WS_MRU",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) [0x06] = "L2_EVICT_LN2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) [0x07] = "0x07",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) [0x08] = "L2_EVICT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) [0x09] = "L2_REFL",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) [0x0a] = "L2_RD",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) [0x0b] = "L2_WR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) [0x0c] = "L2_EVICT_MRU",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) [0x0d] = "L2_SYNC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) [0x0e] = "L2_REFL_ERR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) [0x0f] = "0x0f",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) [0x10] = "L2_INDX_WB_INV",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) [0x11] = "L2_INDX_LD_TAG",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) [0x12] = "L2_INDX_ST_TAG",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) [0x13] = "L2_INDX_ST_DATA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) [0x14] = "L2_INDX_ST_ECC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) [0x15] = "0x15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) [0x16] = "0x16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) [0x17] = "0x17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) [0x18] = "L2_FTCH_AND_LCK",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) [0x19] = "L2_HIT_INV",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) [0x1a] = "L2_HIT_WB_INV",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) [0x1b] = "L2_HIT_WB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) [0x1c] = "0x1c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) [0x1d] = "0x1d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) [0x1e] = "0x1e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) [0x1f] = "0x1f"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static char *cm2_causes[32] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) "None", "GC_WR_ERR", "GC_RD_ERR", "COH_WR_ERR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) "COH_RD_ERR", "MMIO_WR_ERR", "MMIO_RD_ERR", "0x07",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) "0x08", "0x09", "0x0a", "0x0b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) "0x0c", "0x0d", "0x0e", "0x0f",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "0x10", "INTVN_WR_ERR", "INTVN_RD_ERR", "0x13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) "0x14", "0x15", "0x16", "0x17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) "L2_RD_UNCORR", "L2_WR_UNCORR", "L2_CORR", "0x1b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) "0x1c", "0x1d", "0x1e", "0x1f"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static char *cm3_causes[32] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) "0x0", "MP_CORRECTABLE_ECC_ERR", "MP_REQUEST_DECODE_ERR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) "MP_UNCORRECTABLE_ECC_ERR", "MP_PARITY_ERR", "MP_COHERENCE_ERR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) "CMBIU_REQUEST_DECODE_ERR", "CMBIU_PARITY_ERR", "CMBIU_AXI_RESP_ERR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) "0x9", "RBI_BUS_ERR", "0xb", "0xc", "0xd", "0xe", "0xf", "0x10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) "0x11", "0x12", "0x13", "0x14", "0x15", "0x16", "0x17", "0x18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) "0x19", "0x1a", "0x1b", "0x1c", "0x1d", "0x1e", "0x1f"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static DEFINE_PER_CPU_ALIGNED(spinlock_t, cm_core_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static DEFINE_PER_CPU_ALIGNED(unsigned long, cm_core_lock_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) phys_addr_t __mips_cm_phys_base(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 config3 = read_c0_config3();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned long cmgcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Check the CMGCRBase register is implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (!(config3 & MIPS_CONF3_CMGCR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* Read the address from CMGCRBase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) cmgcr = read_c0_cmgcrbase();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return (cmgcr & MIPS_CMGCRF_BASE) << (36 - 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) phys_addr_t mips_cm_phys_base(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) __attribute__((weak, alias("__mips_cm_phys_base")));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) phys_addr_t __mips_cm_l2sync_phys_base(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u32 base_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * If the L2-only sync region is already enabled then leave it at it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * current location.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) base_reg = read_gcr_l2_only_sync_base();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Default to following the CM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return mips_cm_phys_base() + MIPS_CM_GCR_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) phys_addr_t mips_cm_l2sync_phys_base(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) __attribute__((weak, alias("__mips_cm_l2sync_phys_base")));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static void mips_cm_probe_l2sync(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned major_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) phys_addr_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* L2-only sync was introduced with CM major revision 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) major_rev = FIELD_GET(CM_GCR_REV_MAJOR, read_gcr_rev());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (major_rev < 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Find a location for the L2 sync region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) addr = mips_cm_l2sync_phys_base();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) BUG_ON((addr & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE) != addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (!addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* Set the region base address & enable it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) write_gcr_l2_only_sync_base(addr | CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Map the region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) mips_cm_l2sync_base = ioremap(addr, MIPS_CM_L2SYNC_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int mips_cm_probe(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) phys_addr_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u32 base_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * No need to probe again if we have already been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * here before.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (mips_gcr_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) addr = mips_cm_phys_base();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) BUG_ON((addr & CM_GCR_BASE_GCRBASE) != addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (!addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) mips_gcr_base = ioremap(addr, MIPS_CM_GCR_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (!mips_gcr_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* sanity check that we're looking at a CM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) base_reg = read_gcr_base();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if ((base_reg & CM_GCR_BASE_GCRBASE) != addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) pr_err("GCRs appear to have been moved (expected them at 0x%08lx)!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) (unsigned long)addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) mips_gcr_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* set default target to memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) change_gcr_base(CM_GCR_BASE_CMDEFTGT, CM_GCR_BASE_CMDEFTGT_MEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* disable CM regions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) write_gcr_reg0_mask(CM_GCR_REGn_MASK_ADDRMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) write_gcr_reg1_base(CM_GCR_REGn_BASE_BASEADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) write_gcr_reg1_mask(CM_GCR_REGn_MASK_ADDRMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) write_gcr_reg2_base(CM_GCR_REGn_BASE_BASEADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) write_gcr_reg2_mask(CM_GCR_REGn_MASK_ADDRMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) write_gcr_reg3_base(CM_GCR_REGn_BASE_BASEADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) write_gcr_reg3_mask(CM_GCR_REGn_MASK_ADDRMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* probe for an L2-only sync region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) mips_cm_probe_l2sync();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* determine register width for this CM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) mips_cm_is64 = IS_ENABLED(CONFIG_64BIT) && (mips_cm_revision() >= CM_REV_CM3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) for_each_possible_cpu(cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) spin_lock_init(&per_cpu(cm_core_lock, cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) void mips_cm_lock_other(unsigned int cluster, unsigned int core,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned int vp, unsigned int block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned int curr_core, cm_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) cm_rev = mips_cm_revision();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (cm_rev >= CM_REV_CM3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) val = FIELD_PREP(CM3_GCR_Cx_OTHER_CORE, core) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) FIELD_PREP(CM3_GCR_Cx_OTHER_VP, vp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (cm_rev >= CM_REV_CM3_5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) val |= CM_GCR_Cx_OTHER_CLUSTER_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) val |= FIELD_PREP(CM_GCR_Cx_OTHER_CLUSTER, cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) val |= FIELD_PREP(CM_GCR_Cx_OTHER_BLOCK, block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) WARN_ON(cluster != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) WARN_ON(block != CM_GCR_Cx_OTHER_BLOCK_LOCAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * We need to disable interrupts in SMP systems in order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * ensure that we don't interrupt the caller with code which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * may modify the redirect register. We do so here in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * slightly obscure way by using a spin lock, since this has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * the neat property of also catching any nested uses of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * mips_cm_lock_other() leading to a deadlock or a nice warning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * with lockdep enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) spin_lock_irqsave(this_cpu_ptr(&cm_core_lock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) *this_cpu_ptr(&cm_core_lock_flags));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) WARN_ON(cluster != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) WARN_ON(block != CM_GCR_Cx_OTHER_BLOCK_LOCAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * We only have a GCR_CL_OTHER per core in systems with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * CM 2.5 & older, so have to ensure other VP(E)s don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * race with us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) curr_core = cpu_core(¤t_cpu_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) spin_lock_irqsave(&per_cpu(cm_core_lock, curr_core),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) per_cpu(cm_core_lock_flags, curr_core));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) val = FIELD_PREP(CM_GCR_Cx_OTHER_CORENUM, core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) write_gcr_cl_other(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * Ensure the core-other region reflects the appropriate core &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * VP before any accesses to it occur.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) void mips_cm_unlock_other(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) unsigned int curr_core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (mips_cm_revision() < CM_REV_CM3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) curr_core = cpu_core(¤t_cpu_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) spin_unlock_irqrestore(&per_cpu(cm_core_lock, curr_core),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) per_cpu(cm_core_lock_flags, curr_core));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) spin_unlock_irqrestore(this_cpu_ptr(&cm_core_lock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) *this_cpu_ptr(&cm_core_lock_flags));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) void mips_cm_error_report(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u64 cm_error, cm_addr, cm_other;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) unsigned long revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int ocause, cause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) char buf[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (!mips_cm_present())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) revision = mips_cm_revision();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) cm_error = read_gcr_error_cause();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) cm_addr = read_gcr_error_addr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) cm_other = read_gcr_error_mult();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (revision < CM_REV_CM3) { /* CM2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) cause = FIELD_GET(CM_GCR_ERROR_CAUSE_ERRTYPE, cm_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ocause = FIELD_GET(CM_GCR_ERROR_MULT_ERR2ND, cm_other);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (!cause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (cause < 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) unsigned long cca_bits = (cm_error >> 15) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) unsigned long tr_bits = (cm_error >> 12) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) unsigned long cmd_bits = (cm_error >> 7) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) unsigned long stag_bits = (cm_error >> 3) & 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) unsigned long sport_bits = (cm_error >> 0) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) snprintf(buf, sizeof(buf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) "CCA=%lu TR=%s MCmd=%s STag=%lu "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) "SPort=%lu\n", cca_bits, cm2_tr[tr_bits],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) cm2_cmd[cmd_bits], stag_bits, sport_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) } else if (cause < 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* glob state & sresp together */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) unsigned long c3_bits = (cm_error >> 18) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) unsigned long c2_bits = (cm_error >> 15) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) unsigned long c1_bits = (cm_error >> 12) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) unsigned long c0_bits = (cm_error >> 9) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) unsigned long sc_bit = (cm_error >> 8) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) unsigned long cmd_bits = (cm_error >> 3) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) unsigned long sport_bits = (cm_error >> 0) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) snprintf(buf, sizeof(buf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) "C3=%s C2=%s C1=%s C0=%s SC=%s "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) "MCmd=%s SPort=%lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) cm2_core[c3_bits], cm2_core[c2_bits],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) cm2_core[c1_bits], cm2_core[c0_bits],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) sc_bit ? "True" : "False",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) cm2_cmd[cmd_bits], sport_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) unsigned long muc_bit = (cm_error >> 23) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) unsigned long ins_bits = (cm_error >> 18) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) unsigned long arr_bits = (cm_error >> 16) & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) unsigned long dw_bits = (cm_error >> 12) & 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) unsigned long way_bits = (cm_error >> 9) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) unsigned long mway_bit = (cm_error >> 8) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) unsigned long syn_bits = (cm_error >> 0) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) snprintf(buf, sizeof(buf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) "Type=%s%s Instr=%s DW=%lu Way=%lu "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) "MWay=%s Syndrome=0x%02lx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) muc_bit ? "Multi-UC " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) cm2_l2_type[arr_bits],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) cm2_l2_instr[ins_bits], dw_bits, way_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) mway_bit ? "True" : "False", syn_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) pr_err("CM_ERROR=%08llx %s <%s>\n", cm_error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) cm2_causes[cause], buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) pr_err("CM_ADDR =%08llx\n", cm_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) pr_err("CM_OTHER=%08llx %s\n", cm_other, cm2_causes[ocause]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) } else { /* CM3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ulong core_id_bits, vp_id_bits, cmd_bits, cmd_group_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ulong cm3_cca_bits, mcp_bits, cm3_tr_bits, sched_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) cause = FIELD_GET(CM3_GCR_ERROR_CAUSE_ERRTYPE, cm_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ocause = FIELD_GET(CM_GCR_ERROR_MULT_ERR2ND, cm_other);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (!cause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* Used by cause == {1,2,3} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) core_id_bits = (cm_error >> 22) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) vp_id_bits = (cm_error >> 18) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) cmd_bits = (cm_error >> 14) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) cmd_group_bits = (cm_error >> 11) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) cm3_cca_bits = (cm_error >> 8) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) mcp_bits = (cm_error >> 5) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) cm3_tr_bits = (cm_error >> 1) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) sched_bit = cm_error & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (cause == 1 || cause == 3) { /* Tag ECC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) unsigned long tag_ecc = (cm_error >> 57) & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) unsigned long tag_way_bits = (cm_error >> 29) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) unsigned long dword_bits = (cm_error >> 49) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) unsigned long data_way_bits = (cm_error >> 45) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) unsigned long data_sets_bits = (cm_error >> 29) & 0xfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) unsigned long bank_bit = (cm_error >> 28) & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) snprintf(buf, sizeof(buf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) "%s ECC Error: Way=%lu (DWORD=%lu, Sets=%lu)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) "Bank=%lu CoreID=%lu VPID=%lu Command=%s"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) "Command Group=%s CCA=%lu MCP=%d"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) "Transaction type=%s Scheduler=%lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) tag_ecc ? "TAG" : "DATA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) tag_ecc ? (unsigned long)ffs(tag_way_bits) - 1 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) data_way_bits, bank_bit, dword_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) data_sets_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) core_id_bits, vp_id_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) cm3_cmd[cmd_bits],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) cm3_cmd_group[cmd_group_bits],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) cm3_cca_bits, 1 << mcp_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) cm3_tr[cm3_tr_bits], sched_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) } else if (cause == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) unsigned long data_error_type = (cm_error >> 41) & 0xfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) unsigned long data_decode_cmd = (cm_error >> 37) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) unsigned long data_decode_group = (cm_error >> 34) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) unsigned long data_decode_destination_id = (cm_error >> 28) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) snprintf(buf, sizeof(buf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) "Decode Request Error: Type=%lu, Command=%lu"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) "Command Group=%lu Destination ID=%lu"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) "CoreID=%lu VPID=%lu Command=%s"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) "Command Group=%s CCA=%lu MCP=%d"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) "Transaction type=%s Scheduler=%lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) data_error_type, data_decode_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) data_decode_group, data_decode_destination_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) core_id_bits, vp_id_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) cm3_cmd[cmd_bits],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) cm3_cmd_group[cmd_group_bits],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) cm3_cca_bits, 1 << mcp_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) cm3_tr[cm3_tr_bits], sched_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) buf[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) pr_err("CM_ERROR=%llx %s <%s>\n", cm_error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) cm3_causes[cause], buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) pr_err("CM_ADDR =%llx\n", cm_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) pr_err("CM_OTHER=%llx %s\n", cm_other, cm3_causes[ocause]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* reprime cause register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) write_gcr_error_cause(cm_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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