Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2003 Ralf Baechle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Handler for RM7000 extended interrupts.  These are a non-standard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * feature so we handle them separately from standard interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/irq_cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static inline void unmask_rm7k_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	set_c0_intcontrol(0x100 << (d->irq - RM7K_CPU_IRQ_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static inline void mask_rm7k_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	clear_c0_intcontrol(0x100 << (d->irq - RM7K_CPU_IRQ_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static struct irq_chip rm7k_irq_controller = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	.name = "RM7000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	.irq_ack = mask_rm7k_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	.irq_mask = mask_rm7k_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	.irq_mask_ack = mask_rm7k_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	.irq_unmask = unmask_rm7k_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	.irq_eoi = unmask_rm7k_irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) void __init rm7k_cpu_irq_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	int base = RM7K_CPU_IRQ_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	clear_c0_intcontrol(0x00000f00);		/* Mask all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	for (i = base; i < base + 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		irq_set_chip_and_handler(i, &rm7k_irq_controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 					 handle_percpu_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }