Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * A gpio chip driver for TXx9 SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2008 Atsushi Nemoto <anemo@mba.ocn.ne.jp>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/txx9pio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static DEFINE_SPINLOCK(txx9_gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static struct txx9_pio_reg __iomem *txx9_pioptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static int txx9_gpio_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	return !!(__raw_readl(&txx9_pioptr->din) & (1 << offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static void txx9_gpio_set_raw(unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	val = __raw_readl(&txx9_pioptr->dout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		val |= 1 << offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		val &= ~(1 << offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	__raw_writel(val, &txx9_pioptr->dout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static void txx9_gpio_set(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 			  int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	spin_lock_irqsave(&txx9_gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	txx9_gpio_set_raw(offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	mmiowb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	spin_unlock_irqrestore(&txx9_gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static int txx9_gpio_dir_in(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	spin_lock_irqsave(&txx9_gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	__raw_writel(__raw_readl(&txx9_pioptr->dir) & ~(1 << offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		     &txx9_pioptr->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	mmiowb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	spin_unlock_irqrestore(&txx9_gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int txx9_gpio_dir_out(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 			     int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	spin_lock_irqsave(&txx9_gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	txx9_gpio_set_raw(offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	__raw_writel(__raw_readl(&txx9_pioptr->dir) | (1 << offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		     &txx9_pioptr->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	mmiowb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	spin_unlock_irqrestore(&txx9_gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static struct gpio_chip txx9_gpio_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	.get = txx9_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	.set = txx9_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	.direction_input = txx9_gpio_dir_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	.direction_output = txx9_gpio_dir_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	.label = "TXx9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int __init txx9_gpio_init(unsigned long baseaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 			  unsigned int base, unsigned int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 	txx9_pioptr = ioremap(baseaddr, sizeof(struct txx9_pio_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 	if (!txx9_pioptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 	txx9_gpio_chip.base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 	txx9_gpio_chip.ngpio = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 	return gpiochip_add_data(&txx9_gpio_chip, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }