Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Processor capabilities determination functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) xxxx  the Anonymous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 1994 - 2006 Ralf Baechle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2003, 2004  Maciej W. Rozycki
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2001, 2004, 2011, 2012	 MIPS Technologies, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/bugs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/cpu-features.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/cpu-type.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/elf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/fpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include "fpu-probe.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * Get the FPU Implementation/Revision.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static inline unsigned long cpu_get_fpu_id(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	unsigned long tmp, fpu_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	tmp = read_c0_status();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	__enable_fpu(FPU_AS_IS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	fpu_id = read_32bit_cp1_register(CP1_REVISION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	write_c0_status(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	return fpu_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * Check if the CPU has an external FPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) int __cpu_has_fpu(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  * Determine the FCSR mask for FPU hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	unsigned long sr, mask, fcsr, fcsr0, fcsr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	fcsr = c->fpu_csr31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	sr = read_c0_status();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	__enable_fpu(FPU_AS_IS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	fcsr0 = fcsr & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	write_32bit_cp1_register(CP1_STATUS, fcsr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	fcsr0 = read_32bit_cp1_register(CP1_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	fcsr1 = fcsr | ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	write_32bit_cp1_register(CP1_STATUS, fcsr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	fcsr1 = read_32bit_cp1_register(CP1_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	write_32bit_cp1_register(CP1_STATUS, fcsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	write_c0_status(sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  * supported by FPU hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static void cpu_set_fpu_2008(struct cpuinfo_mips *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 			    MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 			    MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			    MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		unsigned long sr, fir, fcsr, fcsr0, fcsr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		sr = read_c0_status();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		__enable_fpu(FPU_AS_IS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		fir = read_32bit_cp1_register(CP1_REVISION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		if (fir & MIPS_FPIR_HAS2008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 			fcsr = read_32bit_cp1_register(CP1_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 			 * MAC2008 toolchain never landed in real world, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 			 * we're only testing whether it can be disabled and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			 *  don't try to enabled it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 					 FPU_CSR_MAC2008);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			write_32bit_cp1_register(CP1_STATUS, fcsr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			fcsr0 = read_32bit_cp1_register(CP1_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 			fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 			write_32bit_cp1_register(CP1_STATUS, fcsr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			fcsr1 = read_32bit_cp1_register(CP1_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 			write_32bit_cp1_register(CP1_STATUS, fcsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			if (c->isa_level & (MIPS_CPU_ISA_M32R2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 					    MIPS_CPU_ISA_M64R2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 				/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 				 * The bit for MAC2008 might be reused by R6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 				 * in future, so we only test for R2-R5.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 				 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 				if (fcsr0 & FPU_CSR_MAC2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 					c->options |= MIPS_CPU_MAC_2008_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			if (!(fcsr0 & FPU_CSR_NAN2008))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 				c->options |= MIPS_CPU_NAN_LEGACY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			if (fcsr1 & FPU_CSR_NAN2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 				c->options |= MIPS_CPU_NAN_2008;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 				c->fpu_msk31 &= ~FPU_CSR_ABS2008;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 				c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 				c->fpu_msk31 &= ~FPU_CSR_NAN2008;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 				c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			c->options |= MIPS_CPU_NAN_LEGACY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		write_c0_status(sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		c->options |= MIPS_CPU_NAN_LEGACY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  * IEEE 754 conformance mode to use.  Affects the NaN encoding and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  * ABS.fmt/NEG.fmt execution mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)  * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  * to support by the FPU emulator according to the IEEE 754 conformance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)  * mode selected.  Note that "relaxed" straps the emulator so that it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)  * allows 2008-NaN binaries even for legacy processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static void cpu_set_nofpu_2008(struct cpuinfo_mips *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	switch (ieee754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	case STRICT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 				    MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 				    MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 				    MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			c->options |= MIPS_CPU_NAN_LEGACY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	case LEGACY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		c->options |= MIPS_CPU_NAN_LEGACY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	case STD2008:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		c->options |= MIPS_CPU_NAN_2008;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	case RELAXED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)  * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)  * according to the "ieee754=" parameter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void cpu_set_nan_2008(struct cpuinfo_mips *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	switch (ieee754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	case STRICT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		mips_use_nan_legacy = !!cpu_has_nan_legacy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		mips_use_nan_2008 = !!cpu_has_nan_2008;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	case LEGACY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		mips_use_nan_legacy = !!cpu_has_nan_legacy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		mips_use_nan_2008 = !cpu_has_nan_legacy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	case STD2008:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		mips_use_nan_legacy = !cpu_has_nan_2008;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		mips_use_nan_2008 = !!cpu_has_nan_2008;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	case RELAXED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		mips_use_nan_legacy = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		mips_use_nan_2008 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)  * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)  * settings:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)  * strict:  accept binaries that request a NaN encoding supported by the FPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)  * legacy:  only accept legacy-NaN binaries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)  * 2008:    only accept 2008-NaN binaries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)  * relaxed: accept any binaries regardless of whether supported by the FPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int __init ieee754_setup(char *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	if (!s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	else if (!strcmp(s, "strict"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		ieee754 = STRICT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	else if (!strcmp(s, "legacy"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		ieee754 = LEGACY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	else if (!strcmp(s, "2008"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		ieee754 = STD2008;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	else if (!strcmp(s, "relaxed"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		ieee754 = RELAXED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	if (!(boot_cpu_data.options & MIPS_CPU_FPU))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		cpu_set_nofpu_2008(&boot_cpu_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	cpu_set_nan_2008(&boot_cpu_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) early_param("ieee754", ieee754_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)  * Set the FIR feature flags for the FPU emulator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			    MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			    MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			    MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		value |= MIPS_FPIR_D | MIPS_FPIR_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			    MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 			    MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	if (c->options & MIPS_CPU_NAN_2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		value |= MIPS_FPIR_HAS2008;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	c->fpu_id = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Determined FPU emulator mask to use for the boot CPU with "nofpu".  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static unsigned int mips_nofpu_msk31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)  * Set options for FPU hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) void cpu_set_fpu_opts(struct cpuinfo_mips *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	c->fpu_id = cpu_get_fpu_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	mips_nofpu_msk31 = c->fpu_msk31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 			    MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 			    MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 			    MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		if (c->fpu_id & MIPS_FPIR_3D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 			c->ases |= MIPS_ASE_MIPS3D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		if (c->fpu_id & MIPS_FPIR_UFRP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 			c->options |= MIPS_CPU_UFR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		if (c->fpu_id & MIPS_FPIR_FREP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 			c->options |= MIPS_CPU_FRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	cpu_set_fpu_fcsr_mask(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	cpu_set_fpu_2008(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	cpu_set_nan_2008(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)  * Set options for the FPU emulator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	c->options &= ~MIPS_CPU_FPU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	c->fpu_msk31 = mips_nofpu_msk31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	cpu_set_nofpu_2008(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	cpu_set_nan_2008(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	cpu_set_nofpu_id(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int mips_fpu_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static int __init fpu_disable(char *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	cpu_set_nofpu_opts(&boot_cpu_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	mips_fpu_disabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) __setup("nofpu", fpu_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)