Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2014 Imagination Technologies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Paul Burton <paul.burton@mips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/binfmts.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/elf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm/cpu-features.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/cpu-info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #ifdef CONFIG_MIPS_FP_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /* Whether to accept legacy-NaN and 2008-NaN user binaries.  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) bool mips_use_nan_legacy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) bool mips_use_nan_2008;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* FPU modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	FP_FRE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	FP_FR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	FP_FR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * struct mode_req - ABI FPU mode requirements
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * @single:	The program being loaded needs an FPU but it will only issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  *		single precision instructions meaning that it can execute in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  *		either FR0 or FR1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * @soft:	The soft(-float) requirement means that the program being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  *		loaded needs has no FPU dependency at all (i.e. it has no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  *		FPU instructions).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * @fr1:	The program being loaded depends on FPU being in FR=1 mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * @frdefault:	The program being loaded depends on the default FPU mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  *		That is FR0 for O32 and FR1 for N32/N64.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * @fre:	The program being loaded depends on FPU with FRE=1. This mode is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  *		a bridge which uses FR=1 whilst still being able to maintain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  *		full compatibility with pre-existing code using the O32 FP32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  *		ABI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * More information about the FP ABIs can be found here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  * https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking#10.4.1._Basic_mode_set-up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) struct mode_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	bool single;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	bool soft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	bool fr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	bool frdefault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	bool fre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static const struct mode_req fpu_reqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	[MIPS_ABI_FP_ANY]    = { true,  true,  true,  true,  true  },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	[MIPS_ABI_FP_DOUBLE] = { false, false, false, true,  true  },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	[MIPS_ABI_FP_SINGLE] = { true,  false, false, false, false },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	[MIPS_ABI_FP_SOFT]   = { false, true,  false, false, false },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	[MIPS_ABI_FP_OLD_64] = { false, false, false, false, false },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	[MIPS_ABI_FP_XX]     = { false, false, true,  true,  true  },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	[MIPS_ABI_FP_64]     = { false, false, true,  false, false },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	[MIPS_ABI_FP_64A]    = { false, false, true,  false, true  }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  * Mode requirements when .MIPS.abiflags is not present in the ELF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  * Not present means that everything is acceptable except FR1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static struct mode_req none_req = { true, true, false, true, true };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) int arch_elf_pt_proc(void *_ehdr, void *_phdr, struct file *elf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		     bool is_interp, struct arch_elf_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		struct elf32_hdr e32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		struct elf64_hdr e64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	} *ehdr = _ehdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct elf32_phdr *phdr32 = _phdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	struct elf64_phdr *phdr64 = _phdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct mips_elf_abiflags_v0 abiflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	bool elf32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	loff_t pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	elf32 = ehdr->e32.e_ident[EI_CLASS] == ELFCLASS32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	flags = elf32 ? ehdr->e32.e_flags : ehdr->e64.e_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	/* Let's see if this is an O32 ELF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	if (elf32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		if (flags & EF_MIPS_FP64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 			 * Set MIPS_ABI_FP_OLD_64 for EF_MIPS_FP64. We will override it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			 * later if needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			if (is_interp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 				state->interp_fp_abi = MIPS_ABI_FP_OLD_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 				state->fp_abi = MIPS_ABI_FP_OLD_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		if (phdr32->p_type != PT_MIPS_ABIFLAGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		if (phdr32->p_filesz < sizeof(abiflags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		pos = phdr32->p_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		if (phdr64->p_type != PT_MIPS_ABIFLAGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		if (phdr64->p_filesz < sizeof(abiflags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		pos = phdr64->p_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	ret = kernel_read(elf, &abiflags, sizeof(abiflags), &pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	if (ret != sizeof(abiflags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	/* Record the required FP ABIs for use by mips_check_elf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	if (is_interp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		state->interp_fp_abi = abiflags.fp_abi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		state->fp_abi = abiflags.fp_abi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int arch_check_elf(void *_ehdr, bool has_interpreter, void *_interp_ehdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		   struct arch_elf_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		struct elf32_hdr e32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		struct elf64_hdr e64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	} *ehdr = _ehdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		struct elf32_hdr e32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		struct elf64_hdr e64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	} *iehdr = _interp_ehdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	struct mode_req prog_req, interp_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	int fp_abi, interp_fp_abi, abi0, abi1, max_abi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	bool elf32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	elf32 = ehdr->e32.e_ident[EI_CLASS] == ELFCLASS32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	flags = elf32 ? ehdr->e32.e_flags : ehdr->e64.e_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	 * Determine the NaN personality, reject the binary if not allowed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	 * Also ensure that any interpreter matches the executable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	if (flags & EF_MIPS_NAN2008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		if (mips_use_nan_2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			state->nan_2008 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			return -ENOEXEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		if (mips_use_nan_legacy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			state->nan_2008 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			return -ENOEXEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (has_interpreter) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		bool ielf32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		u32 iflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		ielf32 = iehdr->e32.e_ident[EI_CLASS] == ELFCLASS32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		iflags = ielf32 ? iehdr->e32.e_flags : iehdr->e64.e_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		if ((flags ^ iflags) & EF_MIPS_NAN2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			return -ELIBBAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	if (!IS_ENABLED(CONFIG_MIPS_O32_FP64_SUPPORT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	fp_abi = state->fp_abi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	if (has_interpreter) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		interp_fp_abi = state->interp_fp_abi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		abi0 = min(fp_abi, interp_fp_abi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		abi1 = max(fp_abi, interp_fp_abi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		abi0 = abi1 = fp_abi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	if (elf32 && !(flags & EF_MIPS_ABI2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		/* Default to a mode capable of running code expecting FR=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		state->overall_fp_mode = cpu_has_mips_r6 ? FP_FRE : FP_FR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		/* Allow all ABIs we know about */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		max_abi = MIPS_ABI_FP_64A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		/* MIPS64 code always uses FR=1, thus the default is easy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		state->overall_fp_mode = FP_FR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		/* Disallow access to the various FPXX & FP64 ABIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		max_abi = MIPS_ABI_FP_SOFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	if ((abi0 > max_abi && abi0 != MIPS_ABI_FP_UNKNOWN) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	    (abi1 > max_abi && abi1 != MIPS_ABI_FP_UNKNOWN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		return -ELIBBAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	/* It's time to determine the FPU mode requirements */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	prog_req = (abi0 == MIPS_ABI_FP_UNKNOWN) ? none_req : fpu_reqs[abi0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	interp_req = (abi1 == MIPS_ABI_FP_UNKNOWN) ? none_req : fpu_reqs[abi1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	 * Check whether the program's and interp's ABIs have a matching FPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	 * mode requirement.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	prog_req.single = interp_req.single && prog_req.single;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	prog_req.soft = interp_req.soft && prog_req.soft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	prog_req.fr1 = interp_req.fr1 && prog_req.fr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	prog_req.frdefault = interp_req.frdefault && prog_req.frdefault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	prog_req.fre = interp_req.fre && prog_req.fre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	 * Determine the desired FPU mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	 * Decision making:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	 * - We want FR_FRE if FRE=1 and both FR=1 and FR=0 are false. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	 *   means that we have a combination of program and interpreter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	 *   that inherently require the hybrid FP mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	 * - If FR1 and FRDEFAULT is true, that means we hit the any-abi or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	 *   fpxx case. This is because, in any-ABI (or no-ABI) we have no FPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	 *   instructions so we don't care about the mode. We will simply use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	 *   the one preferred by the hardware. In fpxx case, that ABI can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	 *   handle both FR=1 and FR=0, so, again, we simply choose the one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	 *   preferred by the hardware. Next, if we only use single-precision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	 *   FPU instructions, and the default ABI FPU mode is not good
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	 *   (ie single + any ABI combination), we set again the FPU mode to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	 *   one is preferred by the hardware. Next, if we know that the code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	 *   will only use single-precision instructions, shown by single being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	 *   true but frdefault being false, then we again set the FPU mode to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	 *   the one that is preferred by the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	 * - We want FP_FR1 if that's the only matching mode and the default one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	 *   is not good.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	 * - Return with -ELIBADD if we can't find a matching FPU mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		state->overall_fp_mode = FP_FRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	else if ((prog_req.fr1 && prog_req.frdefault) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		 (prog_req.single && !prog_req.frdefault))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		/* Make sure 64-bit MIPS III/IV/64R1 will not pick FR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		state->overall_fp_mode = ((raw_current_cpu_data.fpu_id & MIPS_FPIR_F64) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 					  cpu_has_mips_r2_r6) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 					  FP_FR1 : FP_FR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	else if (prog_req.fr1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		state->overall_fp_mode = FP_FR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	else  if (!prog_req.fre && !prog_req.frdefault &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		  !prog_req.fr1 && !prog_req.single && !prog_req.soft)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		return -ELIBBAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static inline void set_thread_fp_mode(int hybrid, int regs32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (hybrid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		set_thread_flag(TIF_HYBRID_FPREGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		clear_thread_flag(TIF_HYBRID_FPREGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (regs32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		set_thread_flag(TIF_32BIT_FPREGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		clear_thread_flag(TIF_32BIT_FPREGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) void mips_set_personality_fp(struct arch_elf_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	 * This function is only ever called for O32 ELFs so we should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	 * not be worried about N32/N64 binaries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	if (!IS_ENABLED(CONFIG_MIPS_O32_FP64_SUPPORT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	switch (state->overall_fp_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	case FP_FRE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		set_thread_fp_mode(1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	case FP_FR0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		set_thread_fp_mode(0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	case FP_FR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		set_thread_fp_mode(0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)  * Select the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)  * in FCSR according to the ELF NaN personality.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) void mips_set_personality_nan(struct arch_elf_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	struct cpuinfo_mips *c = &boot_cpu_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	struct task_struct *t = current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	t->thread.fpu.fcr31 = c->fpu_csr31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	switch (state->nan_2008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		if (!(c->fpu_msk31 & FPU_CSR_NAN2008))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 			t->thread.fpu.fcr31 |= FPU_CSR_NAN2008;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		if (!(c->fpu_msk31 & FPU_CSR_ABS2008))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 			t->thread.fpu.fcr31 |= FPU_CSR_ABS2008;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #endif /* CONFIG_MIPS_FP_SUPPORT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int mips_elf_read_implies_exec(void *elf_ex, int exstack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	if (exstack != EXSTACK_DISABLE_X) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		/* The binary doesn't request a non-executable stack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	if (!cpu_has_rixi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		/* The CPU doesn't support non-executable memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) EXPORT_SYMBOL(mips_elf_read_implies_exec);