Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2000, 2001 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <asm/addrspace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/sibyte/sb1250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/sibyte/sb1250_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/sibyte/sb1250_int.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/sibyte/sb1250_scd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SB1250_HPT_NUM		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SB1250_HPT_VALUE	M_SCD_TIMER_CNT /* max value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  * again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static inline u64 sb1250_hpt_get_cycles(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	addr = IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	count = G_SCD_TIMER_CNT(__raw_readq(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	return SB1250_HPT_VALUE - count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static u64 sb1250_hpt_read(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	return sb1250_hpt_get_cycles();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct clocksource bcm1250_clocksource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	.name	= "bcm1250-counter-3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	.rating = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	.read	= sb1250_hpt_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	.mask	= CLOCKSOURCE_MASK(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static u64 notrace sb1250_read_sched_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	return sb1250_hpt_get_cycles();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) void __init sb1250_clocksource_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	struct clocksource *cs = &bcm1250_clocksource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	/* Setup hpt using timer #3 but do not enable irq for it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	__raw_writeq(0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		     IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 						 R_SCD_TIMER_CFG)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	__raw_writeq(SB1250_HPT_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		     IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 						 R_SCD_TIMER_INIT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	__raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 		     IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 						 R_SCD_TIMER_CFG)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	clocksource_register_hz(cs, V_SCD_TIMER_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	sched_clock_register(sb1250_read_sched_clock, 23, V_SCD_TIMER_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }