Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *  DEC I/O ASIC's counter clocksource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *  Copyright (C) 2008	Yoichi Yuasa <yuasa@linux-mips.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/ds1287.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/dec/ioasic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/dec/ioasic_addrs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static u64 dec_ioasic_hpt_read(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	return ioasic_read(IO_REG_FCTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static struct clocksource clocksource_dec = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	.name		= "dec-ioasic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	.read		= dec_ioasic_hpt_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	.mask		= CLOCKSOURCE_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static u64 notrace dec_ioasic_read_sched_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	return ioasic_read(IO_REG_FCTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int __init dec_ioasic_clocksource_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	unsigned int freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	u32 start, end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	int i = HZ / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	ds1287_timer_state();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	while (!ds1287_timer_state())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	start = dec_ioasic_hpt_read(&clocksource_dec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	while (i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		while (!ds1287_timer_state())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 			;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	end = dec_ioasic_hpt_read(&clocksource_dec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	freq = (end - start) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	/* An early revision of the I/O ASIC didn't have the counter.  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	if (!freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	printk(KERN_INFO "I/O ASIC clock frequency %dHz\n", freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	clocksource_dec.rating = 200 + freq / 10000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	clocksource_register_hz(&clocksource_dec, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	sched_clock_register(dec_ioasic_read_sched_clock, 32, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }