^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Processor capabilities determination functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) xxxx the Anonymous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1994 - 2006 Ralf Baechle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2003, 2004 Maciej W. Rozycki
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/bugs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/cpu-features.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/cpu-type.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/fpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/mipsmtregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/msa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/watch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/elf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/pgtable-bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/spram.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "fpu-probe.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/mach-loongson64/cpucfg-emul.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Hardware capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) unsigned int elf_hwcap __read_mostly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) EXPORT_SYMBOL_GPL(elf_hwcap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static inline unsigned long cpu_get_msa_id(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned long status, msa_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) status = read_c0_status();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) __enable_fpu(FPU_64BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) enable_msa();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) msa_id = read_msa_ir();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) disable_msa();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) write_c0_status(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return msa_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static int mips_dsp_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static int __init dsp_disable(char *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) mips_dsp_disabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) __setup("nodsp", dsp_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static int mips_htw_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static int __init htw_disable(char *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) mips_htw_disabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) cpu_data[0].options &= ~MIPS_CPU_HTW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) write_c0_pwctl(read_c0_pwctl() &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ~(1 << MIPS_PWCTL_PWEN_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) __setup("nohtw", htw_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int mips_ftlb_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int mips_has_ftlb_configured;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) enum ftlb_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) FTLB_EN = 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) FTLB_SET_PROB = 1 << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int __init ftlb_disable(char *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned int config4, mmuextdef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * If the core hasn't done any FTLB configuration, there is nothing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * for us to do here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (!mips_has_ftlb_configured)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* Disable it in the boot cpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (set_ftlb_enable(&cpu_data[0], 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) pr_warn("Can't turn FTLB off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) config4 = read_c0_config4();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Check that FTLB has been disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* MMUSIZEEXT == VTLB ON, FTLB OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* This should never happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) pr_warn("FTLB could not be disabled!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) mips_ftlb_disabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) mips_has_ftlb_configured = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * noftlb is mainly used for debug purposes so print
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * an informative message instead of using pr_debug()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) pr_info("FTLB has been disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * Some of these bits are duplicated in the decode_config4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * once FTLB has been disabled so undo what decode_config4 did.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) cpu_data[0].tlbsizeftlbsets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) cpu_data[0].tlbsizeftlbsets = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) cpu_data[0].tlbsizeftlbways = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) __setup("noftlb", ftlb_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * Check if the CPU has per tc perf counters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static inline void cpu_set_mt_per_tc_perf(struct cpuinfo_mips *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (read_c0_config7() & MTI_CONF7_PTC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) c->options |= MIPS_CPU_MT_PER_TC_PERF_COUNTERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static inline void check_errata(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct cpuinfo_mips *c = ¤t_cpu_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) switch (current_cpu_type()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) case CPU_34K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * Erratum "RPS May Cause Incorrect Instruction Execution"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * This code only handles VPE0, any SMP/RTOS code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * making use of VPE1 will be responsable for that VPE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) void __init check_bugs32(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) check_errata();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * Probe whether cpu has config register by trying to play with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * alternate cache bit and see whether it matters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * It's used by cpu_probe to distinguish between R3000A and R3081.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static inline int cpu_has_confreg(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #ifdef CONFIG_CPU_R3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) extern unsigned long r3k_cache_size(unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned long size1, size2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned long cfg = read_c0_conf();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) size1 = r3k_cache_size(ST0_ISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) write_c0_conf(cfg ^ R30XX_CONF_AC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) size2 = r3k_cache_size(ST0_ISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) write_c0_conf(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return size1 != size2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static inline void set_elf_platform(int cpu, const char *plat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (cpu == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) __elf_platform = plat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static inline void set_elf_base_platform(const char *plat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (__elf_base_platform == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) __elf_base_platform = plat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #ifdef __NEED_VMBITS_PROBE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) write_c0_entryhi(0x3fffffffffffe000ULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) back_to_back_c0_hazard();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) switch (isa) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) case MIPS_CPU_ISA_M64R5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) c->isa_level |= MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) set_elf_base_platform("mips64r5");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) case MIPS_CPU_ISA_M64R2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) set_elf_base_platform("mips64r2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) case MIPS_CPU_ISA_M64R1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) set_elf_base_platform("mips64");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) case MIPS_CPU_ISA_V:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) c->isa_level |= MIPS_CPU_ISA_V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) set_elf_base_platform("mips5");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) case MIPS_CPU_ISA_IV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) c->isa_level |= MIPS_CPU_ISA_IV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) set_elf_base_platform("mips4");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) case MIPS_CPU_ISA_III:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) set_elf_base_platform("mips3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* R6 incompatible with everything else */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) case MIPS_CPU_ISA_M64R6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) set_elf_base_platform("mips64r6");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) case MIPS_CPU_ISA_M32R6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) c->isa_level |= MIPS_CPU_ISA_M32R6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) set_elf_base_platform("mips32r6");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* Break here so we don't add incompatible ISAs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) case MIPS_CPU_ISA_M32R5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) c->isa_level |= MIPS_CPU_ISA_M32R5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) set_elf_base_platform("mips32r5");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) case MIPS_CPU_ISA_M32R2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) c->isa_level |= MIPS_CPU_ISA_M32R2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) set_elf_base_platform("mips32r2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) case MIPS_CPU_ISA_M32R1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) c->isa_level |= MIPS_CPU_ISA_M32R1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) set_elf_base_platform("mips32");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) case MIPS_CPU_ISA_II:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) c->isa_level |= MIPS_CPU_ISA_II;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) set_elf_base_platform("mips2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static char unknown_isa[] = KERN_ERR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) "Unsupported ISA type, c0.config0: %d.";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) unsigned int probability = c->tlbsize / c->tlbsizevtlb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * 0 = All TLBWR instructions go to FTLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * FTLB and 1 goes to the VTLB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * 2 = 7:1: As above with 7:1 ratio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * 3 = 3:1: As above with 3:1 ratio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * Use the linear midpoint as the probability threshold.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (probability >= 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) else if (probability >= 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * So FTLB is less than 4 times bigger than VTLB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * A 3:1 ratio can still be useful though.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) unsigned int config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* It's implementation dependent how the FTLB can be enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) switch (c->cputype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) case CPU_PROAPTIV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) case CPU_P5600:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) case CPU_P6600:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* proAptiv & related cores use Config6 to enable the FTLB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) config = read_c0_config6();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (flags & FTLB_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) config |= MTI_CONF6_FTLBEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) config &= ~MTI_CONF6_FTLBEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (flags & FTLB_SET_PROB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) config &= ~(3 << MTI_CONF6_FTLBP_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) config |= calculate_ftlb_probability(c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) << MTI_CONF6_FTLBP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) write_c0_config6(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) back_to_back_c0_hazard();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) case CPU_I6400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) case CPU_I6500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* There's no way to disable the FTLB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (!(flags & FTLB_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) case CPU_LOONGSON64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* Flush ITLB, DTLB, VTLB and FTLB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* Loongson-3 cores use Config6 to enable the FTLB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) config = read_c0_config6();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (flags & FTLB_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Enable FTLB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) write_c0_config6(config & ~LOONGSON_CONF6_FTLBDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* Disable FTLB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) write_c0_config6(config | LOONGSON_CONF6_FTLBDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int mm_config(struct cpuinfo_mips *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) unsigned int config0, update, mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) config0 = read_c0_config();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) mm = config0 & MIPS_CONF_MM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * It's implementation dependent what type of write-merge is supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * and whether it can be enabled/disabled. If it is settable lets make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * the merging allowed by default. Some platforms might have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * write-through caching unsupported. In this case just ignore the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * CP0.Config.MM bit field value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) switch (c->cputype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) case CPU_24K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) case CPU_34K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) case CPU_74K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) case CPU_P5600:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) case CPU_P6600:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) c->options |= MIPS_CPU_MM_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) update = MIPS_CONF_MM_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) case CPU_1004K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) case CPU_1074K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) case CPU_INTERAPTIV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) case CPU_PROAPTIV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) mm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) update = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (update) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) config0 = (config0 & ~MIPS_CONF_MM) | update;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) write_c0_config(config0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) } else if (mm == MIPS_CONF_MM_SYSAD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) c->options |= MIPS_CPU_MM_SYSAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) } else if (mm == MIPS_CONF_MM_FULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) c->options |= MIPS_CPU_MM_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static inline unsigned int decode_config0(struct cpuinfo_mips *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) unsigned int config0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int isa, mt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) config0 = read_c0_config();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * Look for Standard TLB or Dual VTLB and FTLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) mt = config0 & MIPS_CONF_MT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (mt == MIPS_CONF_MT_TLB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) c->options |= MIPS_CPU_TLB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) else if (mt == MIPS_CONF_MT_FTLB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) isa = (config0 & MIPS_CONF_AT) >> 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) switch (isa) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) switch ((config0 & MIPS_CONF_AR) >> 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) set_isa(c, MIPS_CPU_ISA_M32R1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) set_isa(c, MIPS_CPU_ISA_M32R2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) set_isa(c, MIPS_CPU_ISA_M32R6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) goto unknown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) switch ((config0 & MIPS_CONF_AR) >> 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) set_isa(c, MIPS_CPU_ISA_M64R1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) set_isa(c, MIPS_CPU_ISA_M64R2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) set_isa(c, MIPS_CPU_ISA_M64R6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) goto unknown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) goto unknown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return config0 & MIPS_CONF_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) unknown:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) panic(unknown_isa, config0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static inline unsigned int decode_config1(struct cpuinfo_mips *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) unsigned int config1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) config1 = read_c0_config1();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (config1 & MIPS_CONF1_MD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) c->ases |= MIPS_ASE_MDMX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (config1 & MIPS_CONF1_PC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) c->options |= MIPS_CPU_PERF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (config1 & MIPS_CONF1_WR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) c->options |= MIPS_CPU_WATCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (config1 & MIPS_CONF1_CA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) c->ases |= MIPS_ASE_MIPS16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (config1 & MIPS_CONF1_EP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) c->options |= MIPS_CPU_EJTAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (config1 & MIPS_CONF1_FP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) c->options |= MIPS_CPU_FPU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) c->options |= MIPS_CPU_32FPR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (cpu_has_tlb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) c->tlbsizevtlb = c->tlbsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) c->tlbsizeftlbsets = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return config1 & MIPS_CONF_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static inline unsigned int decode_config2(struct cpuinfo_mips *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) unsigned int config2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) config2 = read_c0_config2();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (config2 & MIPS_CONF2_SL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return config2 & MIPS_CONF_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static inline unsigned int decode_config3(struct cpuinfo_mips *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) unsigned int config3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) config3 = read_c0_config3();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (config3 & MIPS_CONF3_SM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) c->ases |= MIPS_ASE_SMARTMIPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (config3 & MIPS_CONF3_RXI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) c->options |= MIPS_CPU_RIXI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (config3 & MIPS_CONF3_CTXTC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) c->options |= MIPS_CPU_CTXTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (config3 & MIPS_CONF3_DSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) c->ases |= MIPS_ASE_DSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (config3 & MIPS_CONF3_DSP2P) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) c->ases |= MIPS_ASE_DSP2P;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (cpu_has_mips_r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) c->ases |= MIPS_ASE_DSP3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (config3 & MIPS_CONF3_VINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) c->options |= MIPS_CPU_VINT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (config3 & MIPS_CONF3_VEIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) c->options |= MIPS_CPU_VEIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (config3 & MIPS_CONF3_LPA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) c->options |= MIPS_CPU_LPA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (config3 & MIPS_CONF3_MT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) c->ases |= MIPS_ASE_MIPSMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (config3 & MIPS_CONF3_ULRI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) c->options |= MIPS_CPU_ULRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (config3 & MIPS_CONF3_ISA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) c->options |= MIPS_CPU_MICROMIPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (config3 & MIPS_CONF3_VZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) c->ases |= MIPS_ASE_VZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (config3 & MIPS_CONF3_SC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) c->options |= MIPS_CPU_SEGMENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (config3 & MIPS_CONF3_BI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) c->options |= MIPS_CPU_BADINSTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (config3 & MIPS_CONF3_BP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) c->options |= MIPS_CPU_BADINSTRP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (config3 & MIPS_CONF3_MSA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) c->ases |= MIPS_ASE_MSA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (config3 & MIPS_CONF3_PW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) c->htw_seq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) c->options |= MIPS_CPU_HTW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (config3 & MIPS_CONF3_CDMM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) c->options |= MIPS_CPU_CDMM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (config3 & MIPS_CONF3_SP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) c->options |= MIPS_CPU_SP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return config3 & MIPS_CONF_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static inline unsigned int decode_config4(struct cpuinfo_mips *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) unsigned int config4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) unsigned int newcf4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) unsigned int mmuextdef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) unsigned long asid_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) config4 = read_c0_config4();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (cpu_has_tlb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) c->options |= MIPS_CPU_TLBINV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * R6 has dropped the MMUExtDef field from config4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * On R6 the fields always describe the FTLB, and only if it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * present according to Config.MT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (!cpu_has_mips_r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) else if (cpu_has_ftlb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) mmuextdef = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) switch (mmuextdef) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) c->tlbsizevtlb = c->tlbsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) c->tlbsizevtlb +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) c->tlbsize = c->tlbsizevtlb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (mips_ftlb_disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) newcf4 = (config4 & ~ftlb_page) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) (page_size_ftlb(mmuextdef) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) MIPS_CONF4_FTLBPAGESIZE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) write_c0_config4(newcf4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) back_to_back_c0_hazard();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) config4 = read_c0_config4();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (config4 != newcf4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) PAGE_SIZE, config4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* Switch FTLB off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) set_ftlb_enable(c, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) mips_ftlb_disabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) c->tlbsizeftlbsets = 1 <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ((config4 & MIPS_CONF4_FTLBSETS) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) MIPS_CONF4_FTLBSETS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) mips_has_ftlb_configured = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) >> MIPS_CONF4_KSCREXIST_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) asid_mask = MIPS_ENTRYHI_ASID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (config4 & MIPS_CONF4_AE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) asid_mask |= MIPS_ENTRYHI_ASIDX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) set_cpu_asid_mask(c, asid_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * Warn if the computed ASID mask doesn't match the mask the kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * is built for. This may indicate either a serious problem or an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * easy optimisation opportunity, but either way should be addressed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) WARN_ON(asid_mask != cpu_asid_mask(c));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return config4 & MIPS_CONF_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static inline unsigned int decode_config5(struct cpuinfo_mips *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) unsigned int config5, max_mmid_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) unsigned long asid_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) config5 = read_c0_config5();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (cpu_has_mips_r6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (!__builtin_constant_p(cpu_has_mmid) || cpu_has_mmid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) config5 |= MIPS_CONF5_MI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) config5 &= ~MIPS_CONF5_MI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) write_c0_config5(config5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (config5 & MIPS_CONF5_EVA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) c->options |= MIPS_CPU_EVA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (config5 & MIPS_CONF5_MRP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) c->options |= MIPS_CPU_MAAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (config5 & MIPS_CONF5_LLB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) c->options |= MIPS_CPU_RW_LLB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (config5 & MIPS_CONF5_MVH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) c->options |= MIPS_CPU_MVH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) c->options |= MIPS_CPU_VP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (config5 & MIPS_CONF5_CA2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) c->ases |= MIPS_ASE_MIPS16E2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (config5 & MIPS_CONF5_CRCP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) elf_hwcap |= HWCAP_MIPS_CRC32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (cpu_has_mips_r6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* Ensure the write to config5 above takes effect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) back_to_back_c0_hazard();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* Check whether we successfully enabled MMID support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) config5 = read_c0_config5();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (config5 & MIPS_CONF5_MI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) c->options |= MIPS_CPU_MMID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * Warn if we've hardcoded cpu_has_mmid to a value unsuitable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * for the CPU we're running on, or if CPUs in an SMP system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * have inconsistent MMID support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) WARN_ON(!!cpu_has_mmid != !!(config5 & MIPS_CONF5_MI));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (cpu_has_mmid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) write_c0_memorymapid(~0ul);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) back_to_back_c0_hazard();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) asid_mask = read_c0_memorymapid();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * We maintain a bitmap to track MMID allocation, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * need a sensible upper bound on the size of that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) * bitmap. The initial CPU with MMID support (I6500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * supports 16 bit MMIDs, which gives us an 8KiB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * bitmap. The architecture recommends that hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * support 32 bit MMIDs, which would give us a 512MiB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * bitmap - that's too big in most cases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * Cap MMID width at 16 bits for now & we can revisit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * this if & when hardware supports anything wider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) max_mmid_width = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (asid_mask > GENMASK(max_mmid_width - 1, 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) pr_info("Capping MMID width at %d bits",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) max_mmid_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) asid_mask = GENMASK(max_mmid_width - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) set_cpu_asid_mask(c, asid_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return config5 & MIPS_CONF_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static void decode_configs(struct cpuinfo_mips *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) int ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /* MIPS32 or MIPS64 compliant CPU. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) c->scache.flags = MIPS_CACHE_NOT_PRESENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* Enable FTLB if present and not disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) ok = decode_config0(c); /* Read Config registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) BUG_ON(!ok); /* Arch spec violation! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (ok)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) ok = decode_config1(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (ok)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) ok = decode_config2(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (ok)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) ok = decode_config3(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (ok)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ok = decode_config4(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (ok)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) ok = decode_config5(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /* Probe the EBase.WG bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (cpu_has_mips_r2_r6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) u64 ebase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) ebase = cpu_has_mips64r6 ? read_c0_ebase_64()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) : (s32)read_c0_ebase();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (ebase & MIPS_EBASE_WG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* WG bit already set, we can avoid the clumsy probe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) c->options |= MIPS_CPU_EBASE_WG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /* Its UNDEFINED to change EBase while BEV=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) status = read_c0_status();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) write_c0_status(status | ST0_BEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) irq_enable_hazard();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * On pre-r6 cores, this may well clobber the upper bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * of EBase. This is hard to avoid without potentially
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (cpu_has_mips64r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) write_c0_ebase_64(ebase | MIPS_EBASE_WG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) write_c0_ebase(ebase | MIPS_EBASE_WG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) back_to_back_c0_hazard();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /* Restore BEV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) write_c0_status(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (read_c0_ebase() & MIPS_EBASE_WG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) c->options |= MIPS_CPU_EBASE_WG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) write_c0_ebase(ebase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* configure the FTLB write probability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) mips_probe_watch_registers(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #ifndef CONFIG_MIPS_CPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (cpu_has_mips_r2_r6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) unsigned int core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) core = get_ebase_cpunum();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (cpu_has_mipsmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) core >>= fls(core_nvpes()) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) cpu_set_core(c, core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) * Probe for certain guest capabilities by writing config bits and reading back.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * Finally write back the original value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define probe_gc0_config(name, maxconf, bits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) unsigned int tmp; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) tmp = read_gc0_##name(); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) write_gc0_##name(tmp | (bits)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) back_to_back_c0_hazard(); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) maxconf = read_gc0_##name(); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) write_gc0_##name(tmp); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * Probe for dynamic guest capabilities by changing certain config bits and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * reading back to see if they change. Finally write back the original value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) maxconf = read_gc0_##name(); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) write_gc0_##name(maxconf ^ (bits)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) back_to_back_c0_hazard(); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) dynconf = maxconf ^ read_gc0_##name(); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) write_gc0_##name(maxconf); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) maxconf |= dynconf; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) unsigned int config0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) probe_gc0_config(config, config0, MIPS_CONF_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (config0 & MIPS_CONF_M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) c->guest.conf |= BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return config0 & MIPS_CONF_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) unsigned int config1, config1_dyn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) probe_gc0_config_dyn(config1, config1, config1_dyn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) MIPS_CONF1_FP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (config1 & MIPS_CONF1_FP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) c->guest.options |= MIPS_CPU_FPU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (config1_dyn & MIPS_CONF1_FP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) c->guest.options_dyn |= MIPS_CPU_FPU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (config1 & MIPS_CONF1_WR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) c->guest.options |= MIPS_CPU_WATCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (config1_dyn & MIPS_CONF1_WR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) c->guest.options_dyn |= MIPS_CPU_WATCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (config1 & MIPS_CONF1_PC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) c->guest.options |= MIPS_CPU_PERF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (config1_dyn & MIPS_CONF1_PC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) c->guest.options_dyn |= MIPS_CPU_PERF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (config1 & MIPS_CONF_M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) c->guest.conf |= BIT(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return config1 & MIPS_CONF_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) unsigned int config2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) probe_gc0_config(config2, config2, MIPS_CONF_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (config2 & MIPS_CONF_M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) c->guest.conf |= BIT(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return config2 & MIPS_CONF_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) unsigned int config3, config3_dyn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) probe_gc0_config_dyn(config3, config3, config3_dyn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_ULRI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) MIPS_CONF3_CTXTC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (config3 & MIPS_CONF3_CTXTC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) c->guest.options |= MIPS_CPU_CTXTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (config3_dyn & MIPS_CONF3_CTXTC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) c->guest.options_dyn |= MIPS_CPU_CTXTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (config3 & MIPS_CONF3_PW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) c->guest.options |= MIPS_CPU_HTW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (config3 & MIPS_CONF3_ULRI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) c->guest.options |= MIPS_CPU_ULRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (config3 & MIPS_CONF3_SC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) c->guest.options |= MIPS_CPU_SEGMENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (config3 & MIPS_CONF3_BI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) c->guest.options |= MIPS_CPU_BADINSTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (config3 & MIPS_CONF3_BP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) c->guest.options |= MIPS_CPU_BADINSTRP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (config3 & MIPS_CONF3_MSA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) c->guest.ases |= MIPS_ASE_MSA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (config3_dyn & MIPS_CONF3_MSA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) c->guest.ases_dyn |= MIPS_ASE_MSA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (config3 & MIPS_CONF_M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) c->guest.conf |= BIT(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return config3 & MIPS_CONF_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) unsigned int config4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) probe_gc0_config(config4, config4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) MIPS_CONF_M | MIPS_CONF4_KSCREXIST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) >> MIPS_CONF4_KSCREXIST_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (config4 & MIPS_CONF_M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) c->guest.conf |= BIT(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return config4 & MIPS_CONF_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) unsigned int config5, config5_dyn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) probe_gc0_config_dyn(config5, config5, config5_dyn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) MIPS_CONF_M | MIPS_CONF5_MVH | MIPS_CONF5_MRP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (config5 & MIPS_CONF5_MRP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) c->guest.options |= MIPS_CPU_MAAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (config5_dyn & MIPS_CONF5_MRP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) c->guest.options_dyn |= MIPS_CPU_MAAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (config5 & MIPS_CONF5_LLB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) c->guest.options |= MIPS_CPU_RW_LLB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (config5 & MIPS_CONF5_MVH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) c->guest.options |= MIPS_CPU_MVH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (config5 & MIPS_CONF_M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) c->guest.conf |= BIT(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) return config5 & MIPS_CONF_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static inline void decode_guest_configs(struct cpuinfo_mips *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) unsigned int ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) ok = decode_guest_config0(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (ok)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) ok = decode_guest_config1(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (ok)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) ok = decode_guest_config2(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (ok)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) ok = decode_guest_config3(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (ok)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) ok = decode_guest_config4(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (ok)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) decode_guest_config5(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) unsigned int guestctl0, temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) guestctl0 = read_c0_guestctl0();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (guestctl0 & MIPS_GCTL0_G0E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) c->options |= MIPS_CPU_GUESTCTL0EXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (guestctl0 & MIPS_GCTL0_G1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) c->options |= MIPS_CPU_GUESTCTL1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (guestctl0 & MIPS_GCTL0_G2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) c->options |= MIPS_CPU_GUESTCTL2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (!(guestctl0 & MIPS_GCTL0_RAD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) c->options |= MIPS_CPU_GUESTID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) * first, otherwise all data accesses will be fully virtualised
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) * as if they were performed by guest mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) write_c0_guestctl1(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) tlbw_use_hazard();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) back_to_back_c0_hazard();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) temp = read_c0_guestctl0();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (temp & MIPS_GCTL0_DRG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) write_c0_guestctl0(guestctl0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) c->options |= MIPS_CPU_DRG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (cpu_has_guestid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) /* determine the number of bits of GuestID available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) write_c0_guestctl1(MIPS_GCTL1_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) back_to_back_c0_hazard();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) >> MIPS_GCTL1_ID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) write_c0_guestctl1(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /* determine the number of bits of GTOffset available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) write_c0_gtoffset(0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) back_to_back_c0_hazard();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) c->gtoffset_mask = read_c0_gtoffset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) write_c0_gtoffset(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) static inline void cpu_probe_vz(struct cpuinfo_mips *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) cpu_probe_guestctl0(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (cpu_has_guestctl1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) cpu_probe_guestctl1(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) cpu_probe_gtoffset(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) decode_guest_configs(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) | MIPS_CPU_COUNTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) switch (c->processor_id & PRID_IMP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) case PRID_IMP_R2000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) c->cputype = CPU_R2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) __cpu_name[cpu] = "R2000";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) MIPS_CPU_NOFPUEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (__cpu_has_fpu())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) c->options |= MIPS_CPU_FPU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) c->tlbsize = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) case PRID_IMP_R3000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (cpu_has_confreg()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) c->cputype = CPU_R3081E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) __cpu_name[cpu] = "R3081";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) c->cputype = CPU_R3000A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) __cpu_name[cpu] = "R3000A";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) c->cputype = CPU_R3000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) __cpu_name[cpu] = "R3000";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) MIPS_CPU_NOFPUEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (__cpu_has_fpu())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) c->options |= MIPS_CPU_FPU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) c->tlbsize = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) case PRID_IMP_R4000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (read_c0_config() & CONF_SC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if ((c->processor_id & PRID_REV_MASK) >=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) PRID_REV_R4400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) c->cputype = CPU_R4400PC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) __cpu_name[cpu] = "R4400PC";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) c->cputype = CPU_R4000PC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) __cpu_name[cpu] = "R4000PC";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) int cca = read_c0_config() & CONF_CM_CMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) int mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) * SC and MC versions can't be reliably told apart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) * but only the latter support coherent caching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) * modes so assume the firmware has set the KSEG0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) * coherency attribute reasonably (if uncached, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) * assume SC).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) switch (cca) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) case CONF_CM_CACHABLE_CE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) case CONF_CM_CACHABLE_COW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) case CONF_CM_CACHABLE_CUW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) mc = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) mc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if ((c->processor_id & PRID_REV_MASK) >=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) PRID_REV_R4400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) set_isa(c, MIPS_CPU_ISA_III);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) c->fpu_msk31 |= FPU_CSR_CONDX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) MIPS_CPU_WATCH | MIPS_CPU_VCE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) MIPS_CPU_LLSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) c->tlbsize = 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) case PRID_IMP_VR41XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) set_isa(c, MIPS_CPU_ISA_III);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) c->fpu_msk31 |= FPU_CSR_CONDX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) c->options = R4K_OPTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) c->tlbsize = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) switch (c->processor_id & 0xf0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) case PRID_REV_VR4111:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) c->cputype = CPU_VR4111;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) __cpu_name[cpu] = "NEC VR4111";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) case PRID_REV_VR4121:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) c->cputype = CPU_VR4121;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) __cpu_name[cpu] = "NEC VR4121";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) case PRID_REV_VR4122:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if ((c->processor_id & 0xf) < 0x3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) c->cputype = CPU_VR4122;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) __cpu_name[cpu] = "NEC VR4122";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) c->cputype = CPU_VR4181A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) __cpu_name[cpu] = "NEC VR4181A";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) case PRID_REV_VR4130:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if ((c->processor_id & 0xf) < 0x4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) c->cputype = CPU_VR4131;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) __cpu_name[cpu] = "NEC VR4131";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) c->cputype = CPU_VR4133;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) c->options |= MIPS_CPU_LLSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) __cpu_name[cpu] = "NEC VR4133";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) c->cputype = CPU_VR41XX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) __cpu_name[cpu] = "NEC Vr41xx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) case PRID_IMP_R4600:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) c->cputype = CPU_R4600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) __cpu_name[cpu] = "R4600";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) set_isa(c, MIPS_CPU_ISA_III);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) c->fpu_msk31 |= FPU_CSR_CONDX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) MIPS_CPU_LLSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) c->tlbsize = 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) case PRID_IMP_R4650:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) * This processor doesn't have an MMU, so it's not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) * "real easy" to run Linux on it. It is left purely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) * for documentation. Commented out because it shares
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) * it's c0_prid id number with the TX3900.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) c->cputype = CPU_R4650;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) __cpu_name[cpu] = "R4650";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) set_isa(c, MIPS_CPU_ISA_III);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) c->fpu_msk31 |= FPU_CSR_CONDX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) c->tlbsize = 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) case PRID_IMP_TX39:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) c->cputype = CPU_TX3927;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) __cpu_name[cpu] = "TX3927";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) c->tlbsize = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) switch (c->processor_id & PRID_REV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) case PRID_REV_TX3912:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) c->cputype = CPU_TX3912;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) __cpu_name[cpu] = "TX3912";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) c->tlbsize = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) case PRID_REV_TX3922:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) c->cputype = CPU_TX3922;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) __cpu_name[cpu] = "TX3922";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) c->tlbsize = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) case PRID_IMP_R4700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) c->cputype = CPU_R4700;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) __cpu_name[cpu] = "R4700";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) set_isa(c, MIPS_CPU_ISA_III);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) c->fpu_msk31 |= FPU_CSR_CONDX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) MIPS_CPU_LLSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) c->tlbsize = 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) case PRID_IMP_TX49:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) c->cputype = CPU_TX49XX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) __cpu_name[cpu] = "R49XX";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) set_isa(c, MIPS_CPU_ISA_III);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) c->fpu_msk31 |= FPU_CSR_CONDX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) c->options = R4K_OPTS | MIPS_CPU_LLSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (!(c->processor_id & 0x08))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) c->tlbsize = 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) case PRID_IMP_R5000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) c->cputype = CPU_R5000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) __cpu_name[cpu] = "R5000";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) set_isa(c, MIPS_CPU_ISA_IV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) MIPS_CPU_LLSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) c->tlbsize = 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) case PRID_IMP_R5500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) c->cputype = CPU_R5500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) __cpu_name[cpu] = "R5500";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) set_isa(c, MIPS_CPU_ISA_IV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) MIPS_CPU_WATCH | MIPS_CPU_LLSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) c->tlbsize = 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) case PRID_IMP_NEVADA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) c->cputype = CPU_NEVADA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) __cpu_name[cpu] = "Nevada";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) set_isa(c, MIPS_CPU_ISA_IV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) c->tlbsize = 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) case PRID_IMP_RM7000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) c->cputype = CPU_RM7000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) __cpu_name[cpu] = "RM7000";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) set_isa(c, MIPS_CPU_ISA_IV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) MIPS_CPU_LLSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) * Undocumented RM7000: Bit 29 in the info register of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) * the RM7000 v2.0 indicates if the TLB has 48 or 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) * entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) * 29 1 => 64 entry JTLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) * 0 => 48 entry JTLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) case PRID_IMP_R10000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) c->cputype = CPU_R10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) __cpu_name[cpu] = "R10000";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) set_isa(c, MIPS_CPU_ISA_IV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) MIPS_CPU_FPU | MIPS_CPU_32FPR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) MIPS_CPU_LLSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) c->tlbsize = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) case PRID_IMP_R12000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) c->cputype = CPU_R12000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) __cpu_name[cpu] = "R12000";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) set_isa(c, MIPS_CPU_ISA_IV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) MIPS_CPU_FPU | MIPS_CPU_32FPR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) MIPS_CPU_LLSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) c->tlbsize = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) write_c0_r10k_diag(read_c0_r10k_diag() | R10K_DIAG_E_GHIST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) case PRID_IMP_R14000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) if (((c->processor_id >> 4) & 0x0f) > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) c->cputype = CPU_R16000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) __cpu_name[cpu] = "R16000";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) c->cputype = CPU_R14000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) __cpu_name[cpu] = "R14000";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) set_isa(c, MIPS_CPU_ISA_IV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) MIPS_CPU_FPU | MIPS_CPU_32FPR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) MIPS_CPU_LLSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) c->tlbsize = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) write_c0_r10k_diag(read_c0_r10k_diag() | R10K_DIAG_E_GHIST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) case PRID_IMP_LOONGSON_64C: /* Loongson-2/3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) switch (c->processor_id & PRID_REV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) case PRID_REV_LOONGSON2E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) c->cputype = CPU_LOONGSON2EF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) __cpu_name[cpu] = "ICT Loongson-2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) set_elf_platform(cpu, "loongson2e");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) set_isa(c, MIPS_CPU_ISA_III);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) c->fpu_msk31 |= FPU_CSR_CONDX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) case PRID_REV_LOONGSON2F:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) c->cputype = CPU_LOONGSON2EF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) __cpu_name[cpu] = "ICT Loongson-2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) set_elf_platform(cpu, "loongson2f");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) set_isa(c, MIPS_CPU_ISA_III);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) c->fpu_msk31 |= FPU_CSR_CONDX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) case PRID_REV_LOONGSON3A_R1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) c->cputype = CPU_LOONGSON64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) __cpu_name[cpu] = "ICT Loongson-3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) set_elf_platform(cpu, "loongson3a");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) set_isa(c, MIPS_CPU_ISA_M64R1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) MIPS_ASE_LOONGSON_EXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) case PRID_REV_LOONGSON3B_R1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) case PRID_REV_LOONGSON3B_R2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) c->cputype = CPU_LOONGSON64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) __cpu_name[cpu] = "ICT Loongson-3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) set_elf_platform(cpu, "loongson3b");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) set_isa(c, MIPS_CPU_ISA_M64R1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) MIPS_ASE_LOONGSON_EXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) c->options = R4K_OPTS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) MIPS_CPU_FPU | MIPS_CPU_LLSC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) MIPS_CPU_32FPR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) c->tlbsize = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) set_cpu_asid_mask(c, MIPS_ENTRYHI_ASID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) c->writecombine = _CACHE_UNCACHED_ACCELERATED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) case PRID_IMP_LOONGSON_32: /* Loongson-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) decode_configs(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) c->cputype = CPU_LOONGSON32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) switch (c->processor_id & PRID_REV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) case PRID_REV_LOONGSON1B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) __cpu_name[cpu] = "Loongson 1B";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) c->writecombine = _CACHE_UNCACHED_ACCELERATED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) switch (c->processor_id & PRID_IMP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) case PRID_IMP_QEMU_GENERIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) c->writecombine = _CACHE_UNCACHED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) c->cputype = CPU_QEMU_GENERIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) __cpu_name[cpu] = "MIPS GENERIC QEMU";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) case PRID_IMP_4KC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) c->cputype = CPU_4KC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) c->writecombine = _CACHE_UNCACHED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) __cpu_name[cpu] = "MIPS 4Kc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) case PRID_IMP_4KEC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) case PRID_IMP_4KECR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) c->cputype = CPU_4KEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) c->writecombine = _CACHE_UNCACHED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) __cpu_name[cpu] = "MIPS 4KEc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) case PRID_IMP_4KSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) case PRID_IMP_4KSD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) c->cputype = CPU_4KSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) c->writecombine = _CACHE_UNCACHED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) __cpu_name[cpu] = "MIPS 4KSc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) case PRID_IMP_5KC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) c->cputype = CPU_5KC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) c->writecombine = _CACHE_UNCACHED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) __cpu_name[cpu] = "MIPS 5Kc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) case PRID_IMP_5KE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) c->cputype = CPU_5KE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) c->writecombine = _CACHE_UNCACHED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) __cpu_name[cpu] = "MIPS 5KE";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) case PRID_IMP_20KC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) c->cputype = CPU_20KC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) c->writecombine = _CACHE_UNCACHED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) __cpu_name[cpu] = "MIPS 20Kc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) case PRID_IMP_24K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) c->cputype = CPU_24K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) c->writecombine = _CACHE_UNCACHED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) __cpu_name[cpu] = "MIPS 24Kc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) case PRID_IMP_24KE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) c->cputype = CPU_24K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) c->writecombine = _CACHE_UNCACHED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) __cpu_name[cpu] = "MIPS 24KEc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) case PRID_IMP_25KF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) c->cputype = CPU_25KF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) c->writecombine = _CACHE_UNCACHED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) __cpu_name[cpu] = "MIPS 25Kc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) case PRID_IMP_34K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) c->cputype = CPU_34K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) c->writecombine = _CACHE_UNCACHED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) __cpu_name[cpu] = "MIPS 34Kc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) cpu_set_mt_per_tc_perf(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) case PRID_IMP_74K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) c->cputype = CPU_74K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) c->writecombine = _CACHE_UNCACHED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) __cpu_name[cpu] = "MIPS 74Kc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) case PRID_IMP_M14KC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) c->cputype = CPU_M14KC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) c->writecombine = _CACHE_UNCACHED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) __cpu_name[cpu] = "MIPS M14Kc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) case PRID_IMP_M14KEC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) c->cputype = CPU_M14KEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) c->writecombine = _CACHE_UNCACHED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) __cpu_name[cpu] = "MIPS M14KEc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) case PRID_IMP_1004K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) c->cputype = CPU_1004K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) c->writecombine = _CACHE_UNCACHED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) __cpu_name[cpu] = "MIPS 1004Kc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) cpu_set_mt_per_tc_perf(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) case PRID_IMP_1074K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) c->cputype = CPU_1074K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) c->writecombine = _CACHE_UNCACHED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) __cpu_name[cpu] = "MIPS 1074Kc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) case PRID_IMP_INTERAPTIV_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) c->cputype = CPU_INTERAPTIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) __cpu_name[cpu] = "MIPS interAptiv";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) cpu_set_mt_per_tc_perf(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) case PRID_IMP_INTERAPTIV_MP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) c->cputype = CPU_INTERAPTIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) __cpu_name[cpu] = "MIPS interAptiv (multi)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) cpu_set_mt_per_tc_perf(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) case PRID_IMP_PROAPTIV_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) c->cputype = CPU_PROAPTIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) __cpu_name[cpu] = "MIPS proAptiv";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) case PRID_IMP_PROAPTIV_MP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) c->cputype = CPU_PROAPTIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) __cpu_name[cpu] = "MIPS proAptiv (multi)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) case PRID_IMP_P5600:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) c->cputype = CPU_P5600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) __cpu_name[cpu] = "MIPS P5600";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) case PRID_IMP_P6600:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) c->cputype = CPU_P6600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) __cpu_name[cpu] = "MIPS P6600";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) case PRID_IMP_I6400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) c->cputype = CPU_I6400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) __cpu_name[cpu] = "MIPS I6400";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) case PRID_IMP_I6500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) c->cputype = CPU_I6500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) __cpu_name[cpu] = "MIPS I6500";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) case PRID_IMP_M5150:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) c->cputype = CPU_M5150;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) __cpu_name[cpu] = "MIPS M5150";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) case PRID_IMP_M6250:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) c->cputype = CPU_M6250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) __cpu_name[cpu] = "MIPS M6250";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) decode_configs(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) spram_config();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) mm_config(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) switch (__get_cpu_type(c->cputype)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) case CPU_M5150:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) case CPU_P5600:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) set_isa(c, MIPS_CPU_ISA_M32R5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) case CPU_I6500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) case CPU_I6400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) c->options |= MIPS_CPU_SHARED_FTLB_RAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) /* Recent MIPS cores use the implementation-dependent ExcCode 16 for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) * cache/FTLB parity exceptions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) switch (__get_cpu_type(c->cputype)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) case CPU_PROAPTIV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) case CPU_P5600:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) case CPU_P6600:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) case CPU_I6400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) case CPU_I6500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) c->options |= MIPS_CPU_FTLBPAREX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) decode_configs(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) switch (c->processor_id & PRID_IMP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) case PRID_IMP_AU1_REV1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) case PRID_IMP_AU1_REV2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) c->cputype = CPU_ALCHEMY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) switch ((c->processor_id >> 24) & 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) __cpu_name[cpu] = "Au1000";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) __cpu_name[cpu] = "Au1500";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) __cpu_name[cpu] = "Au1100";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) __cpu_name[cpu] = "Au1550";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) __cpu_name[cpu] = "Au1200";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) if ((c->processor_id & PRID_REV_MASK) == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) __cpu_name[cpu] = "Au1250";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) __cpu_name[cpu] = "Au1210";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) __cpu_name[cpu] = "Au1xxx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) decode_configs(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) c->writecombine = _CACHE_UNCACHED_ACCELERATED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) switch (c->processor_id & PRID_IMP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) case PRID_IMP_SB1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) c->cputype = CPU_SB1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) __cpu_name[cpu] = "SiByte SB1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) /* FPU in pass1 is known to have issues. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) if ((c->processor_id & PRID_REV_MASK) < 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) case PRID_IMP_SB1A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) c->cputype = CPU_SB1A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) __cpu_name[cpu] = "SiByte SB1A";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) decode_configs(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) switch (c->processor_id & PRID_IMP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) case PRID_IMP_SR71000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) c->cputype = CPU_SR71000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) __cpu_name[cpu] = "Sandcraft SR71000";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) c->scache.ways = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) c->tlbsize = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) decode_configs(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) switch (c->processor_id & PRID_IMP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) case PRID_IMP_PR4450:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) c->cputype = CPU_PR4450;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) __cpu_name[cpu] = "Philips PR4450";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) set_isa(c, MIPS_CPU_ISA_M32R1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) decode_configs(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) switch (c->processor_id & PRID_IMP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) case PRID_IMP_BMIPS32_REV4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) case PRID_IMP_BMIPS32_REV8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) c->cputype = CPU_BMIPS32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) __cpu_name[cpu] = "Broadcom BMIPS32";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) set_elf_platform(cpu, "bmips32");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) case PRID_IMP_BMIPS3300:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) case PRID_IMP_BMIPS3300_ALT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) case PRID_IMP_BMIPS3300_BUG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) c->cputype = CPU_BMIPS3300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) __cpu_name[cpu] = "Broadcom BMIPS3300";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) set_elf_platform(cpu, "bmips3300");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) case PRID_IMP_BMIPS43XX: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) int rev = c->processor_id & PRID_REV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) if (rev >= PRID_REV_BMIPS4380_LO &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) rev <= PRID_REV_BMIPS4380_HI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) c->cputype = CPU_BMIPS4380;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) __cpu_name[cpu] = "Broadcom BMIPS4380";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) set_elf_platform(cpu, "bmips4380");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) c->options |= MIPS_CPU_RIXI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) c->cputype = CPU_BMIPS4350;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) __cpu_name[cpu] = "Broadcom BMIPS4350";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) set_elf_platform(cpu, "bmips4350");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) case PRID_IMP_BMIPS5000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) case PRID_IMP_BMIPS5200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) c->cputype = CPU_BMIPS5000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) __cpu_name[cpu] = "Broadcom BMIPS5200";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) __cpu_name[cpu] = "Broadcom BMIPS5000";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) set_elf_platform(cpu, "bmips5000");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) decode_configs(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) switch (c->processor_id & PRID_IMP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) case PRID_IMP_CAVIUM_CN38XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) case PRID_IMP_CAVIUM_CN31XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) case PRID_IMP_CAVIUM_CN30XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) c->cputype = CPU_CAVIUM_OCTEON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) __cpu_name[cpu] = "Cavium Octeon";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) goto platform;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) case PRID_IMP_CAVIUM_CN58XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) case PRID_IMP_CAVIUM_CN56XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) case PRID_IMP_CAVIUM_CN50XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) case PRID_IMP_CAVIUM_CN52XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) c->cputype = CPU_CAVIUM_OCTEON_PLUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) __cpu_name[cpu] = "Cavium Octeon+";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) platform:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) set_elf_platform(cpu, "octeon");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) case PRID_IMP_CAVIUM_CN61XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) case PRID_IMP_CAVIUM_CN63XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) case PRID_IMP_CAVIUM_CN66XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) case PRID_IMP_CAVIUM_CN68XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) case PRID_IMP_CAVIUM_CNF71XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) c->cputype = CPU_CAVIUM_OCTEON2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) __cpu_name[cpu] = "Cavium Octeon II";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) set_elf_platform(cpu, "octeon2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) case PRID_IMP_CAVIUM_CN70XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) case PRID_IMP_CAVIUM_CN73XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) case PRID_IMP_CAVIUM_CNF75XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) case PRID_IMP_CAVIUM_CN78XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) c->cputype = CPU_CAVIUM_OCTEON3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) __cpu_name[cpu] = "Cavium Octeon III";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) set_elf_platform(cpu, "octeon3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) printk(KERN_INFO "Unknown Octeon chip!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) c->cputype = CPU_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) #ifdef CONFIG_CPU_LOONGSON64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) #include <loongson_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) static inline void decode_cpucfg(struct cpuinfo_mips *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) u32 cfg1 = read_cpucfg(LOONGSON_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) u32 cfg2 = read_cpucfg(LOONGSON_CFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) u32 cfg3 = read_cpucfg(LOONGSON_CFG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) if (cfg1 & LOONGSON_CFG1_MMI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) c->ases |= MIPS_ASE_LOONGSON_MMI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) if (cfg2 & LOONGSON_CFG2_LEXT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) c->ases |= MIPS_ASE_LOONGSON_EXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) if (cfg2 & LOONGSON_CFG2_LEXT2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) c->ases |= MIPS_ASE_LOONGSON_EXT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) if (cfg2 & LOONGSON_CFG2_LSPW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) c->options |= MIPS_CPU_LDPTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) c->guest.options |= MIPS_CPU_LDPTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) if (cfg3 & LOONGSON_CFG3_LCAMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) c->ases |= MIPS_ASE_LOONGSON_CAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) /* All Loongson processors covered here define ExcCode 16 as GSExc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) c->options |= MIPS_CPU_GSEXCEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) switch (c->processor_id & PRID_IMP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) case PRID_IMP_LOONGSON_64R: /* Loongson-64 Reduced */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) switch (c->processor_id & PRID_REV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) case PRID_REV_LOONGSON2K_R1_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) case PRID_REV_LOONGSON2K_R1_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) case PRID_REV_LOONGSON2K_R1_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) case PRID_REV_LOONGSON2K_R1_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) c->cputype = CPU_LOONGSON64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) __cpu_name[cpu] = "Loongson-2K";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) set_elf_platform(cpu, "gs264e");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) set_isa(c, MIPS_CPU_ISA_M64R2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_EXT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) MIPS_ASE_LOONGSON_EXT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) case PRID_IMP_LOONGSON_64C: /* Loongson-3 Classic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) switch (c->processor_id & PRID_REV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) case PRID_REV_LOONGSON3A_R2_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) case PRID_REV_LOONGSON3A_R2_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) c->cputype = CPU_LOONGSON64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) __cpu_name[cpu] = "ICT Loongson-3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) set_elf_platform(cpu, "loongson3a");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) set_isa(c, MIPS_CPU_ISA_M64R2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) case PRID_REV_LOONGSON3A_R3_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) case PRID_REV_LOONGSON3A_R3_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) c->cputype = CPU_LOONGSON64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) __cpu_name[cpu] = "ICT Loongson-3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) set_elf_platform(cpu, "loongson3a");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) set_isa(c, MIPS_CPU_ISA_M64R2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) * Loongson-3 Classic did not implement MIPS standard TLBINV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) * but implemented TLBINVF and EHINV. As currently we're only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) * using these two features, enable MIPS_CPU_TLBINV as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) * Also some early Loongson-3A2000 had wrong TLB type in Config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) * register, we correct it here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is incomplete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) case PRID_IMP_LOONGSON_64G:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) c->cputype = CPU_LOONGSON64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) __cpu_name[cpu] = "ICT Loongson-3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) set_elf_platform(cpu, "loongson3a");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) set_isa(c, MIPS_CPU_ISA_M64R2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) decode_cpucfg(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) panic("Unknown Loongson Processor ID!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) decode_configs(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) decode_configs(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) * XBurst misses a config2 register, so config3 decode was skipped in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) * decode_configs().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) decode_config3(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) /* XBurst does not implement the CP0 counter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) c->options &= ~MIPS_CPU_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) BUG_ON(__builtin_constant_p(cpu_has_counter) && cpu_has_counter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) /* XBurst has virtually tagged icache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) c->icache.flags |= MIPS_CACHE_VTAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) switch (c->processor_id & PRID_IMP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) /* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) case PRID_IMP_XBURST_REV1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) * The XBurst core by default attempts to avoid branch target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) * buffer lookups by detecting & special casing loops. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) * feature will cause BogoMIPS and lpj calculate in error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) * Set cp0 config7 bit 4 to disable this feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) set_c0_config7(MIPS_CONF7_BTB_LOOP_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) switch (c->processor_id & PRID_COMP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) * The config0 register in the XBurst CPUs with a processor ID of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) * PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) * but they don't actually support this ISA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) case PRID_COMP_INGENIC_D0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) c->isa_level &= ~MIPS_CPU_ISA_M32R2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) /* FPU is not properly detected on JZ4760(B). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) if (c->processor_id == 0x2ed0024f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) c->options |= MIPS_CPU_FPU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) * The config0 register in the XBurst CPUs with a processor ID of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) * PRID_COMP_INGENIC_D0 or PRID_COMP_INGENIC_D1 has an abandoned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) * huge page tlb mode, this mode is not compatible with the MIPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) * standard, it will cause tlbmiss and into an infinite loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) * (line 21 in the tlb-funcs.S) when starting the init process.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) * After chip reset, the default is HPTLB mode, Write 0xa9000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) * to cp0 register 5 sel 4 to switch back to VTLB mode to prevent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) * getting stuck.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) case PRID_COMP_INGENIC_D1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) write_c0_page_ctrl(XBURST_PAGECTRL_HPTLB_DIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) /* XBurst®1 with MXU2.0 SIMD ISA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) case PRID_IMP_XBURST_REV2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) /* Ingenic uses the WA bit to achieve write-combine memory writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) c->writecombine = _CACHE_CACHABLE_WA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) c->cputype = CPU_XBURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) __cpu_name[cpu] = "Ingenic XBurst";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) /* XBurst®2 with MXU2.1 SIMD ISA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) case PRID_IMP_XBURST2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) c->cputype = CPU_XBURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) __cpu_name[cpu] = "Ingenic XBurst II";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) panic("Unknown Ingenic Processor ID!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) decode_configs(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) c->cputype = CPU_ALCHEMY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) __cpu_name[cpu] = "Au1300";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) /* following stuff is not for Alchemy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) c->options = (MIPS_CPU_TLB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) MIPS_CPU_4KEX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) MIPS_CPU_COUNTER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) MIPS_CPU_DIVEC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) MIPS_CPU_WATCH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) MIPS_CPU_EJTAG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) MIPS_CPU_LLSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) switch (c->processor_id & PRID_IMP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) case PRID_IMP_NETLOGIC_XLP2XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) case PRID_IMP_NETLOGIC_XLP9XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) case PRID_IMP_NETLOGIC_XLP5XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) c->cputype = CPU_XLP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) __cpu_name[cpu] = "Broadcom XLPII";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) case PRID_IMP_NETLOGIC_XLP8XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) case PRID_IMP_NETLOGIC_XLP3XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) c->cputype = CPU_XLP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) __cpu_name[cpu] = "Netlogic XLP";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) case PRID_IMP_NETLOGIC_XLR732:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) case PRID_IMP_NETLOGIC_XLR716:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) case PRID_IMP_NETLOGIC_XLR532:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) case PRID_IMP_NETLOGIC_XLR308:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) case PRID_IMP_NETLOGIC_XLR532C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) case PRID_IMP_NETLOGIC_XLR516C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) case PRID_IMP_NETLOGIC_XLR508C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) case PRID_IMP_NETLOGIC_XLR308C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) c->cputype = CPU_XLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) __cpu_name[cpu] = "Netlogic XLR";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) case PRID_IMP_NETLOGIC_XLS608:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) case PRID_IMP_NETLOGIC_XLS408:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) case PRID_IMP_NETLOGIC_XLS404:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) case PRID_IMP_NETLOGIC_XLS208:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) case PRID_IMP_NETLOGIC_XLS204:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) case PRID_IMP_NETLOGIC_XLS108:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) case PRID_IMP_NETLOGIC_XLS104:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) case PRID_IMP_NETLOGIC_XLS616B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) case PRID_IMP_NETLOGIC_XLS608B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) case PRID_IMP_NETLOGIC_XLS416B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) case PRID_IMP_NETLOGIC_XLS412B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) case PRID_IMP_NETLOGIC_XLS408B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) case PRID_IMP_NETLOGIC_XLS404B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) c->cputype = CPU_XLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) __cpu_name[cpu] = "Netlogic XLS";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) pr_info("Unknown Netlogic chip id [%02x]!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) c->processor_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) c->cputype = CPU_XLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) if (c->cputype == CPU_XLP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) set_isa(c, MIPS_CPU_ISA_M64R2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) /* This will be updated again after all threads are woken up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) set_isa(c, MIPS_CPU_ISA_M64R1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) c->kscratch_mask = 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) /* For use by uaccess.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) u64 __ua_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) EXPORT_SYMBOL(__ua_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) const char *__cpu_name[NR_CPUS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) const char *__elf_platform;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) const char *__elf_base_platform;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) void cpu_probe(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) struct cpuinfo_mips *c = ¤t_cpu_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) unsigned int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) * Set a default elf platform, cpu probe may later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) * overwrite it with a more precise value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) set_elf_platform(cpu, "mips");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) c->processor_id = PRID_IMP_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) c->fpu_id = FPIR_IMP_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) c->cputype = CPU_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) c->writecombine = _CACHE_UNCACHED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) c->fpu_csr31 = FPU_CSR_RN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) c->processor_id = read_c0_prid();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) switch (c->processor_id & PRID_COMP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) case PRID_COMP_LEGACY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) cpu_probe_legacy(c, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) case PRID_COMP_MIPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) cpu_probe_mips(c, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) case PRID_COMP_ALCHEMY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) cpu_probe_alchemy(c, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) case PRID_COMP_SIBYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) cpu_probe_sibyte(c, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) case PRID_COMP_BROADCOM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) cpu_probe_broadcom(c, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) case PRID_COMP_SANDCRAFT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) cpu_probe_sandcraft(c, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) case PRID_COMP_NXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) cpu_probe_nxp(c, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) case PRID_COMP_CAVIUM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) cpu_probe_cavium(c, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) case PRID_COMP_LOONGSON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) cpu_probe_loongson(c, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) case PRID_COMP_INGENIC_13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) case PRID_COMP_INGENIC_D0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) case PRID_COMP_INGENIC_D1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) case PRID_COMP_INGENIC_E1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) cpu_probe_ingenic(c, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) case PRID_COMP_NETLOGIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) cpu_probe_netlogic(c, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) BUG_ON(!__cpu_name[cpu]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) BUG_ON(c->cputype == CPU_UNKNOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) * Platform code can force the cpu type to optimize code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) * generation. In that case be sure the cpu type is correctly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) * manually setup otherwise it could trigger some nasty bugs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) BUG_ON(current_cpu_type() != c->cputype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) if (cpu_has_rixi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) /* Enable the RIXI exceptions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) set_c0_pagegrain(PG_IEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) back_to_back_c0_hazard();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) /* Verify the IEC bit is set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) if (read_c0_pagegrain() & PG_IEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) c->options |= MIPS_CPU_RIXIEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) if (mips_fpu_disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) c->options &= ~MIPS_CPU_FPU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) if (mips_dsp_disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) if (mips_htw_disabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) c->options &= ~MIPS_CPU_HTW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) write_c0_pwctl(read_c0_pwctl() &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) ~(1 << MIPS_PWCTL_PWEN_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) if (c->options & MIPS_CPU_FPU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) cpu_set_fpu_opts(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) cpu_set_nofpu_opts(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) if (cpu_has_mips_r2_r6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) /* R2 has Performance Counter Interrupt indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) c->options |= MIPS_CPU_PCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) c->srsets = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) if (cpu_has_mips_r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) elf_hwcap |= HWCAP_MIPS_R6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) if (cpu_has_msa) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) c->msa_id = cpu_get_msa_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) WARN(c->msa_id & MSA_IR_WRPF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) "Vector register partitioning unimplemented!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) elf_hwcap |= HWCAP_MIPS_MSA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) if (cpu_has_mips16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) elf_hwcap |= HWCAP_MIPS_MIPS16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) if (cpu_has_mdmx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) elf_hwcap |= HWCAP_MIPS_MDMX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) if (cpu_has_mips3d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) elf_hwcap |= HWCAP_MIPS_MIPS3D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) if (cpu_has_smartmips)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) elf_hwcap |= HWCAP_MIPS_SMARTMIPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) if (cpu_has_dsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) elf_hwcap |= HWCAP_MIPS_DSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) if (cpu_has_dsp2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) elf_hwcap |= HWCAP_MIPS_DSP2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) if (cpu_has_dsp3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) elf_hwcap |= HWCAP_MIPS_DSP3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) if (cpu_has_mips16e2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) elf_hwcap |= HWCAP_MIPS_MIPS16E2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) if (cpu_has_loongson_mmi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) elf_hwcap |= HWCAP_LOONGSON_MMI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) if (cpu_has_loongson_ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) elf_hwcap |= HWCAP_LOONGSON_EXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) if (cpu_has_loongson_ext2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) elf_hwcap |= HWCAP_LOONGSON_EXT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) if (cpu_has_vz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) cpu_probe_vz(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) cpu_probe_vmbits(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) /* Synthesize CPUCFG data if running on Loongson processors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) * no-op otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) * This looks at previously probed features, so keep this at bottom.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) loongson3_cpucfg_synthesize_data(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) if (cpu == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) __ua_limit = ~((1ull << cpu_vmbits) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) void cpu_report(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) struct cpuinfo_mips *c = ¤t_cpu_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) pr_info("CPU%d revision is: %08x (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) smp_processor_id(), c->processor_id, cpu_name_string());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) if (c->options & MIPS_CPU_FPU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) if (cpu_has_msa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) pr_info("MSA revision is: %08x\n", c->msa_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) /* Ensure the core number fits in the field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) WARN_ON(cluster > (MIPS_GLOBALNUMBER_CLUSTER >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) MIPS_GLOBALNUMBER_CLUSTER_SHF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) /* Ensure the core number fits in the field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) WARN_ON(core > (MIPS_GLOBALNUMBER_CORE >> MIPS_GLOBALNUMBER_CORE_SHF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) /* Ensure the VP(E) ID fits in the field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) WARN_ON(vpe > (MIPS_GLOBALNUMBER_VP >> MIPS_GLOBALNUMBER_VP_SHF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) /* Ensure we're not using VP(E)s without support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) WARN_ON(vpe && !IS_ENABLED(CONFIG_MIPS_MT_SMP) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) !IS_ENABLED(CONFIG_CPU_MIPSR6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags