Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2013 Imagination Technologies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Paul Burton <paul.burton@mips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <asm/addrspace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <asm/asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <asm/asmmacro.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <asm/cacheops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm/eva.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/mipsmtregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define GCR_CPC_BASE_OFS	0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define GCR_CL_COHERENCE_OFS	0x2008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define GCR_CL_ID_OFS		0x2028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define CPC_CL_VC_STOP_OFS	0x2020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define CPC_CL_VC_RUN_OFS	0x2028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) .extern mips_cm_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) .set noreorder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) # define STATUS_BITDEPS		ST0_KX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) # define STATUS_BITDEPS		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #ifdef CONFIG_MIPS_CPS_NS16550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define DUMP_EXCEP(name)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	PTR_LA	a0, 8f;			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	jal	mips_cps_bev_dump;	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	 nop;				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	TEXT(name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #else /* !CONFIG_MIPS_CPS_NS16550 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define DUMP_EXCEP(name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #endif /* !CONFIG_MIPS_CPS_NS16550 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	 * Set dest to non-zero if the core supports the MT ASE, else zero. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	 * MT is not supported then branch to nomt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	.macro	has_mt	dest, nomt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	mfc0	\dest, CP0_CONFIG, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	bgez	\dest, \nomt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	 mfc0	\dest, CP0_CONFIG, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	bgez	\dest, \nomt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	 mfc0	\dest, CP0_CONFIG, 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	andi	\dest, \dest, MIPS_CONF3_MT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	beqz	\dest, \nomt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	 * Set dest to non-zero if the core supports MIPSr6 multithreading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	 * (ie. VPs), else zero. If MIPSr6 multithreading is not supported then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	 * branch to nomt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	.macro	has_vp	dest, nomt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	mfc0	\dest, CP0_CONFIG, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	bgez	\dest, \nomt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	 mfc0	\dest, CP0_CONFIG, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	bgez	\dest, \nomt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	 mfc0	\dest, CP0_CONFIG, 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	bgez	\dest, \nomt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	 mfc0	\dest, CP0_CONFIG, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	bgez	\dest, \nomt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	 mfc0	\dest, CP0_CONFIG, 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	andi	\dest, \dest, MIPS_CONF5_VP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	beqz	\dest, \nomt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	/* Calculate an uncached address for the CM GCRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	.macro	cmgcrb	dest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	.set	push
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.set	noat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	MFC0	$1, CP0_CMGCRBASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	PTR_SLL	$1, $1, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	PTR_LI	\dest, UNCAC_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	PTR_ADDU \dest, \dest, $1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	.set	pop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) .section .text.cps-vec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) .balign 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) LEAF(mips_cps_core_entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	 * These first 4 bytes will be patched by cps_smp_setup to load the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	 * CCA to use into register s0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	.word	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	/* Check whether we're here due to an NMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	mfc0	k0, CP0_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	and	k0, k0, ST0_NMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	beqz	k0, not_nmi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	/* This is an NMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	PTR_LA	k0, nmi_handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	jr	k0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) not_nmi:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	/* Setup Cause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	li	t0, CAUSEF_IV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	mtc0	t0, CP0_CAUSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	/* Setup Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	li	t0, ST0_CU1 | ST0_CU0 | ST0_BEV | STATUS_BITDEPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	mtc0	t0, CP0_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	/* Skip cache & coherence setup if we're already coherent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	cmgcrb	v1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	lw	s7, GCR_CL_COHERENCE_OFS(v1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	bnez	s7, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	/* Initialize the L1 caches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	jal	mips_cps_cache_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	/* Enter the coherent domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	li	t0, 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	sw	t0, GCR_CL_COHERENCE_OFS(v1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	ehb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	/* Set Kseg0 CCA to that in s0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 1:	mfc0	t0, CP0_CONFIG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	ori	t0, 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	xori	t0, 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	or	t0, t0, s0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	mtc0	t0, CP0_CONFIG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	ehb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	/* Jump to kseg0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	PTR_LA	t0, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	jr	t0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	 * We're up, cached & coherent. Perform any EVA initialization necessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	 * before we access memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 1:	eva_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	/* Retrieve boot configuration pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	jal	mips_cps_get_bootcfg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	/* Skip core-level init if we started up coherent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	bnez	s7, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	/* Perform any further required core-level initialisation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	jal	mips_cps_core_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	 * Boot any other VPEs within this core that should be online, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	 * deactivate this VPE if it should be offline.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	move	a1, t9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	jal	mips_cps_boot_vpes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	 move	a0, v0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	/* Off we go! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 1:	PTR_L	t1, VPEBOOTCFG_PC(v1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	PTR_L	gp, VPEBOOTCFG_GP(v1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	PTR_L	sp, VPEBOOTCFG_SP(v1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	jr	t1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	END(mips_cps_core_entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .org 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) LEAF(excep_tlbfill)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	DUMP_EXCEP("TLB Fill")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	b	.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	END(excep_tlbfill)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .org 0x280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) LEAF(excep_xtlbfill)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	DUMP_EXCEP("XTLB Fill")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	b	.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	END(excep_xtlbfill)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .org 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) LEAF(excep_cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	DUMP_EXCEP("Cache")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	b	.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	END(excep_cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .org 0x380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) LEAF(excep_genex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	DUMP_EXCEP("General")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	b	.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	END(excep_genex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .org 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) LEAF(excep_intex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	DUMP_EXCEP("Interrupt")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	b	.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	END(excep_intex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .org 0x480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) LEAF(excep_ejtag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	PTR_LA	k0, ejtag_debug_handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	jr	k0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	END(excep_ejtag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) LEAF(mips_cps_core_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #ifdef CONFIG_MIPS_MT_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	/* Check that the core implements the MT ASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	has_mt	t0, 3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	.set	push
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	.set	MIPS_ISA_LEVEL_RAW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	.set	mt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	/* Only allow 1 TC per VPE to execute... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	dmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	/* ...and for the moment only 1 VPE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	dvpe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	PTR_LA	t1, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	jr.hb	t1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	/* Enter VPE configuration state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 1:	mfc0	t0, CP0_MVPCONTROL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	ori	t0, t0, MVPCONTROL_VPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	mtc0	t0, CP0_MVPCONTROL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	/* Retrieve the number of VPEs within the core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	mfc0	t0, CP0_MVPCONF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	srl	t0, t0, MVPCONF0_PVPE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	andi	t0, t0, (MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	addiu	ta3, t0, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	/* If there's only 1, we're done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	beqz	t0, 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	/* Loop through each VPE within this core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	li	ta1, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 1:	/* Operate on the appropriate TC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	mtc0	ta1, CP0_VPECONTROL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	ehb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	/* Bind TC to VPE (1:1 TC:VPE mapping) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	mttc0	ta1, CP0_TCBIND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	/* Set exclusive TC, non-active, master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	li	t0, VPECONF0_MVP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	sll	t1, ta1, VPECONF0_XTC_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	or	t0, t0, t1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	mttc0	t0, CP0_VPECONF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	/* Set TC non-active, non-allocatable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	mttc0	zero, CP0_TCSTATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	/* Set TC halted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	li	t0, TCHALT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	mttc0	t0, CP0_TCHALT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	/* Next VPE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	addiu	ta1, ta1, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	slt	t0, ta1, ta3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	bnez	t0, 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	/* Leave VPE configuration state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 2:	mfc0	t0, CP0_MVPCONTROL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	xori	t0, t0, MVPCONTROL_VPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	mtc0	t0, CP0_MVPCONTROL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 3:	.set	pop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	jr	ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	END(mips_cps_core_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)  * mips_cps_get_bootcfg() - retrieve boot configuration pointers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)  * Returns: pointer to struct core_boot_config in v0, pointer to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)  *          struct vpe_boot_config in v1, VPE ID in t9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) LEAF(mips_cps_get_bootcfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	/* Calculate a pointer to this cores struct core_boot_config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	cmgcrb	t0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	lw	t0, GCR_CL_ID_OFS(t0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	li	t1, COREBOOTCFG_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	mul	t0, t0, t1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	PTR_LA	t1, mips_cps_core_bootcfg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	PTR_L	t1, 0(t1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	PTR_ADDU v0, t0, t1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	/* Calculate this VPEs ID. If the core doesn't support MT use 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	li	t9, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #if defined(CONFIG_CPU_MIPSR6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	has_vp	ta2, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	 * Assume non-contiguous numbering. Perhaps some day we'll need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	 * to handle contiguous VP numbering, but no such systems yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	 * exist.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	mfc0	t9, CP0_GLOBALNUMBER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	andi	t9, t9, MIPS_GLOBALNUMBER_VP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #elif defined(CONFIG_MIPS_MT_SMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	has_mt	ta2, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	/* Find the number of VPEs present in the core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	mfc0	t1, CP0_MVPCONF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	srl	t1, t1, MVPCONF0_PVPE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	andi	t1, t1, MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	addiu	t1, t1, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	/* Calculate a mask for the VPE ID from EBase.CPUNum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	clz	t1, t1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	li	t2, 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	subu	t1, t2, t1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	li	t2, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	sll	t1, t2, t1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	addiu	t1, t1, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	/* Retrieve the VPE ID from EBase.CPUNum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	mfc0	t9, $15, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	and	t9, t9, t1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 1:	/* Calculate a pointer to this VPEs struct vpe_boot_config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	li	t1, VPEBOOTCFG_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	mul	v1, t9, t1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	PTR_L	ta3, COREBOOTCFG_VPECONFIG(v0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	PTR_ADDU v1, v1, ta3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	jr	ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	END(mips_cps_get_bootcfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) LEAF(mips_cps_boot_vpes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	lw	ta2, COREBOOTCFG_VPEMASK(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	PTR_L	ta3, COREBOOTCFG_VPECONFIG(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #if defined(CONFIG_CPU_MIPSR6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	has_vp	t0, 5f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	/* Find base address of CPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	cmgcrb	t3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	PTR_L	t1, GCR_CPC_BASE_OFS(t3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	PTR_LI	t2, ~0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	and	t1, t1, t2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	PTR_LI	t2, UNCAC_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	PTR_ADD	t1, t1, t2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	/* Start any other VPs that ought to be running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	PTR_S	ta2, CPC_CL_VC_RUN_OFS(t1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	/* Ensure this VP stops running if it shouldn't be */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	not	ta2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	PTR_S	ta2, CPC_CL_VC_STOP_OFS(t1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	ehb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #elif defined(CONFIG_MIPS_MT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	/* If the core doesn't support MT then return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	has_mt	t0, 5f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	/* Enter VPE configuration state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	.set	push
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	.set	MIPS_ISA_LEVEL_RAW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	.set	mt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	dvpe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	.set	pop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	PTR_LA	t1, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	jr.hb	t1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 1:	mfc0	t1, CP0_MVPCONTROL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	ori	t1, t1, MVPCONTROL_VPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	mtc0	t1, CP0_MVPCONTROL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	ehb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	/* Loop through each VPE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	move	t8, ta2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	li	ta1, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	/* Check whether the VPE should be running. If not, skip it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 1:	andi	t0, ta2, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	beqz	t0, 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	/* Operate on the appropriate TC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	mfc0	t0, CP0_VPECONTROL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	ori	t0, t0, VPECONTROL_TARGTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	xori	t0, t0, VPECONTROL_TARGTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	or	t0, t0, ta1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	mtc0	t0, CP0_VPECONTROL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	ehb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	.set	push
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	.set	MIPS_ISA_LEVEL_RAW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	.set	mt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	/* Skip the VPE if its TC is not halted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	mftc0	t0, CP0_TCHALT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	beqz	t0, 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	/* Calculate a pointer to the VPEs struct vpe_boot_config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	li	t0, VPEBOOTCFG_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	mul	t0, t0, ta1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	addu	t0, t0, ta3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	/* Set the TC restart PC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	lw	t1, VPEBOOTCFG_PC(t0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	mttc0	t1, CP0_TCRESTART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	/* Set the TC stack pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	lw	t1, VPEBOOTCFG_SP(t0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	mttgpr	t1, sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	/* Set the TC global pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	lw	t1, VPEBOOTCFG_GP(t0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	mttgpr	t1, gp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	/* Copy config from this VPE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	mfc0	t0, CP0_CONFIG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	mttc0	t0, CP0_CONFIG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	 * Copy the EVA config from this VPE if the CPU supports it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	 * CONFIG3 must exist to be running MT startup - just read it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	mfc0	t0, CP0_CONFIG, 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	and	t0, t0, MIPS_CONF3_SC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	beqz	t0, 3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	mfc0    t0, CP0_SEGCTL0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	mttc0	t0, CP0_SEGCTL0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	mfc0    t0, CP0_SEGCTL1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	mttc0	t0, CP0_SEGCTL1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	mfc0    t0, CP0_SEGCTL2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	mttc0	t0, CP0_SEGCTL2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	/* Ensure no software interrupts are pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	mttc0	zero, CP0_CAUSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	mttc0	zero, CP0_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	/* Set TC active, not interrupt exempt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	mftc0	t0, CP0_TCSTATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	li	t1, ~TCSTATUS_IXMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	and	t0, t0, t1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	ori	t0, t0, TCSTATUS_A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	mttc0	t0, CP0_TCSTATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	/* Clear the TC halt bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	mttc0	zero, CP0_TCHALT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	/* Set VPE active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	mftc0	t0, CP0_VPECONF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	ori	t0, t0, VPECONF0_VPA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	mttc0	t0, CP0_VPECONF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	/* Next VPE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 2:	srl	ta2, ta2, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	addiu	ta1, ta1, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	bnez	ta2, 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	/* Leave VPE configuration state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	mfc0	t1, CP0_MVPCONTROL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	xori	t1, t1, MVPCONTROL_VPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	mtc0	t1, CP0_MVPCONTROL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	ehb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	evpe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	.set	pop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	/* Check whether this VPE is meant to be running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	li	t0, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	sll	t0, t0, a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	and	t0, t0, t8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	bnez	t0, 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	/* This VPE should be offline, halt the TC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	li	t0, TCHALT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	mtc0	t0, CP0_TCHALT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	PTR_LA	t0, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 1:	jr.hb	t0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #endif /* CONFIG_MIPS_MT_SMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	/* Return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 5:	jr	ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	END(mips_cps_boot_vpes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) LEAF(mips_cps_cache_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	 * Clear the bits used to index the caches. Note that the architecture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 	 * dictates that writing to any of TagLo or TagHi selects 0 or 2 should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	 * be valid for all MIPS32 CPUs, even those for which said writes are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	 * unnecessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	mtc0	zero, CP0_TAGLO, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	mtc0	zero, CP0_TAGHI, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	mtc0	zero, CP0_TAGLO, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	mtc0	zero, CP0_TAGHI, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	ehb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	/* Primary cache configuration is indicated by Config1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	mfc0	v0, CP0_CONFIG, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 	/* Detect I-cache line size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	_EXT	t0, v0, MIPS_CONF1_IL_SHF, MIPS_CONF1_IL_SZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	beqz	t0, icache_done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	 li	t1, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 	sllv	t0, t1, t0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	/* Detect I-cache size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	_EXT	t1, v0, MIPS_CONF1_IS_SHF, MIPS_CONF1_IS_SZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 	xori	t2, t1, 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 	beqz	t2, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	 li	t3, 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	addiu	t1, t1, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	sllv	t1, t3, t1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 1:	/* At this point t1 == I-cache sets per way */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 	_EXT	t2, v0, MIPS_CONF1_IA_SHF, MIPS_CONF1_IA_SZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 	addiu	t2, t2, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 	mul	t1, t1, t0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 	mul	t1, t1, t2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 	li	a0, CKSEG0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 	PTR_ADD	a1, a0, t1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 1:	cache	Index_Store_Tag_I, 0(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 	PTR_ADD	a0, a0, t0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 	bne	a0, a1, 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) icache_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 	/* Detect D-cache line size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 	_EXT	t0, v0, MIPS_CONF1_DL_SHF, MIPS_CONF1_DL_SZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 	beqz	t0, dcache_done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 	 li	t1, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 	sllv	t0, t1, t0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 	/* Detect D-cache size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 	_EXT	t1, v0, MIPS_CONF1_DS_SHF, MIPS_CONF1_DS_SZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 	xori	t2, t1, 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 	beqz	t2, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 	 li	t3, 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 	addiu	t1, t1, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 	sllv	t1, t3, t1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 1:	/* At this point t1 == D-cache sets per way */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 	_EXT	t2, v0, MIPS_CONF1_DA_SHF, MIPS_CONF1_DA_SZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 	addiu	t2, t2, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 	mul	t1, t1, t0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 	mul	t1, t1, t2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 	li	a0, CKSEG0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 	PTR_ADDU a1, a0, t1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 	PTR_SUBU a1, a1, t0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 1:	cache	Index_Store_Tag_D, 0(a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 	bne	a0, a1, 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 	 PTR_ADD a0, a0, t0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) dcache_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 	jr	ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 	END(mips_cps_cache_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #if defined(CONFIG_MIPS_CPS_PM) && defined(CONFIG_CPU_PM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 	/* Calculate a pointer to this CPUs struct mips_static_suspend_state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 	.macro	psstate	dest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 	.set	push
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 	.set	noat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 	lw	$1, TI_CPU(gp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 	sll	$1, $1, LONGLOG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 	PTR_LA	\dest, __per_cpu_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 	addu	$1, $1, \dest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 	lw	$1, 0($1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 	PTR_LA	\dest, cps_cpu_state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 	addu	\dest, \dest, $1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 	.set	pop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) LEAF(mips_cps_pm_save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 	/* Save CPU state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 	SUSPEND_SAVE_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 	psstate	t1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 	SUSPEND_SAVE_STATIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 	jr	v0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 	END(mips_cps_pm_save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) LEAF(mips_cps_pm_restore)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 	/* Restore CPU state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 	psstate	t1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 	RESUME_RESTORE_STATIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 	RESUME_RESTORE_REGS_RETURN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 	END(mips_cps_pm_restore)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #endif /* CONFIG_MIPS_CPS_PM && CONFIG_CPU_PM */