Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2015 Imagination Technologies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Paul Burton <paul.burton@mips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <asm/addrspace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <asm/asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <asm/regdef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/serial_reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define UART_TX_OFS	(UART_TX << CONFIG_MIPS_CPS_NS16550_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define UART_LSR_OFS	(UART_LSR << CONFIG_MIPS_CPS_NS16550_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #if CONFIG_MIPS_CPS_NS16550_WIDTH == 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) # define UART_L		lb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) # define UART_S		sb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #elif CONFIG_MIPS_CPS_NS16550_WIDTH == 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) # define UART_L		lh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) # define UART_S		sh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #elif CONFIG_MIPS_CPS_NS16550_WIDTH == 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) # define UART_L		lw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) # define UART_S		sw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) # define UART_L		lb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) # define UART_S		sb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * _mips_cps_putc() - write a character to the UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * @a0: ASCII character to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * @t9: UART base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) LEAF(_mips_cps_putc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 1:	UART_L		t0, UART_LSR_OFS(t9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	andi		t0, t0, UART_LSR_TEMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	beqz		t0, 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	UART_S		a0, UART_TX_OFS(t9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	jr		ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	END(_mips_cps_putc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * _mips_cps_puts() - write a string to the UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  * @a0: pointer to NULL-terminated ASCII string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  * @t9: UART base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  * Write a null-terminated ASCII string to the UART.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) NESTED(_mips_cps_puts, 0, ra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	move		s7, ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	move		s6, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 1:	lb		a0, 0(s6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	beqz		a0, 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	jal		_mips_cps_putc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	PTR_ADDIU	s6, s6, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	b		1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 2:	jr		s7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	END(_mips_cps_puts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  * _mips_cps_putx4 - write a 4b hex value to the UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  * @a0: the 4b value to write to the UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  * @t9: UART base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  * Write a single hexadecimal character to the UART.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) NESTED(_mips_cps_putx4, 0, ra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	andi		a0, a0, 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	li		t0, '0'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	blt		a0, 10, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	li		t0, 'a'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	addiu		a0, a0, -10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 1:	addu		a0, a0, t0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	b		_mips_cps_putc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	END(_mips_cps_putx4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  * _mips_cps_putx8 - write an 8b hex value to the UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  * @a0: the 8b value to write to the UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  * @t9: UART base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  * Write an 8 bit value (ie. 2 hexadecimal characters) to the UART.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) NESTED(_mips_cps_putx8, 0, ra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	move		s3, ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	move		s2, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	srl		a0, a0, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	jal		_mips_cps_putx4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	move		a0, s2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	move		ra, s3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	b		_mips_cps_putx4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	END(_mips_cps_putx8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  * _mips_cps_putx16 - write a 16b hex value to the UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  * @a0: the 16b value to write to the UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  * @t9: UART base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  * Write a 16 bit value (ie. 4 hexadecimal characters) to the UART.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) NESTED(_mips_cps_putx16, 0, ra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	move		s5, ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	move		s4, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	srl		a0, a0, 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	jal		_mips_cps_putx8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	move		a0, s4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	move		ra, s5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	b		_mips_cps_putx8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	END(_mips_cps_putx16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  * _mips_cps_putx32 - write a 32b hex value to the UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  * @a0: the 32b value to write to the UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)  * @t9: UART base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)  * Write a 32 bit value (ie. 8 hexadecimal characters) to the UART.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) NESTED(_mips_cps_putx32, 0, ra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	move		s7, ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	move		s6, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	srl		a0, a0, 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	jal		_mips_cps_putx16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	move		a0, s6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	move		ra, s7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	b		_mips_cps_putx16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	END(_mips_cps_putx32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)  * _mips_cps_putx64 - write a 64b hex value to the UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)  * @a0: the 64b value to write to the UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)  * @t9: UART base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)  * Write a 64 bit value (ie. 16 hexadecimal characters) to the UART.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) NESTED(_mips_cps_putx64, 0, ra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	move		sp, ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	move		s8, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	dsrl32		a0, a0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	jal		_mips_cps_putx32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	move		a0, s8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	move		ra, sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	b		_mips_cps_putx32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	END(_mips_cps_putx64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define _mips_cps_putxlong _mips_cps_putx64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #else /* !CONFIG_64BIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define _mips_cps_putxlong _mips_cps_putx32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #endif /* !CONFIG_64BIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)  * mips_cps_bev_dump() - dump relevant exception state to UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)  * @a0: pointer to NULL-terminated ASCII string naming the exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  * Write information that may be useful in debugging an exception to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  * UART configured by CONFIG_MIPS_CPS_NS16550_*. As this BEV exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  * will only be run if something goes horribly wrong very early during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  * the bringup of a core and it is very likely to be unsafe to perform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)  * memory accesses at that point (cache state indeterminate, EVA may not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)  * be configured, coherence may be disabled) let alone have a stack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)  * this is all written in assembly using only registers & unmapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)  * uncached access to the UART registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) LEAF(mips_cps_bev_dump)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	move		s0, ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	move		s1, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	li		t9, CKSEG1ADDR(CONFIG_MIPS_CPS_NS16550_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	PTR_LA		a0, str_newline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	jal		_mips_cps_puts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	PTR_LA		a0, str_bev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	jal		_mips_cps_puts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	move		a0, s1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	jal		_mips_cps_puts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	PTR_LA		a0, str_newline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	jal		_mips_cps_puts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	PTR_LA		a0, str_newline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	jal		_mips_cps_puts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define DUMP_COP0_REG(reg, name, sz, _mfc0)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	PTR_LA		a0, 8f;				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	jal		_mips_cps_puts;			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	_mfc0		a0, reg;			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	jal		_mips_cps_putx##sz;		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	PTR_LA		a0, str_newline;		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	jal		_mips_cps_puts;			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	TEXT(name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	DUMP_COP0_REG(CP0_CAUSE,    "Cause:    0x", 32, mfc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	DUMP_COP0_REG(CP0_STATUS,   "Status:   0x", 32, mfc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	DUMP_COP0_REG(CP0_EBASE,    "EBase:    0x", long, MFC0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	DUMP_COP0_REG(CP0_BADVADDR, "BadVAddr: 0x", long, MFC0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	DUMP_COP0_REG(CP0_BADINSTR, "BadInstr: 0x", 32, mfc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	PTR_LA		a0, str_newline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	jal		_mips_cps_puts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	jr		s0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	END(mips_cps_bev_dump)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .pushsection	.data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) str_bev: .asciiz "BEV Exception: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) str_newline: .asciiz "\r\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .popsection