^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Based on linux/arch/mips/kernel/cevt-r4k.c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * linux/arch/mips/jmr3927/rbhma3100/setup.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright 2001 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2000-2001 Toshiba Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2007 MIPS Technologies, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/txx9tmr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TCR_BASE (TXx9_TMTCR_CCDE | TXx9_TMTCR_CRE | TXx9_TMTCR_TMODE_ITVL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TIMER_CCD 0 /* 1/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TIMER_CLK(imclk) ((imclk) / (2 << TIMER_CCD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct txx9_clocksource {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct clocksource cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct txx9_tmr_reg __iomem *tmrptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static u64 txx9_cs_read(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct txx9_clocksource *txx9_cs =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) container_of(cs, struct txx9_clocksource, cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) return __raw_readl(&txx9_cs->tmrptr->trr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Use 1 bit smaller width to use full bits in that width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TXX9_CLOCKSOURCE_BITS (TXX9_TIMER_BITS - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static struct txx9_clocksource txx9_clocksource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .cs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .name = "TXx9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .rating = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .read = txx9_cs_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .mask = CLOCKSOURCE_MASK(TXX9_CLOCKSOURCE_BITS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .flags = CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static u64 notrace txx9_read_sched_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return __raw_readl(&txx9_clocksource.tmrptr->trr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) void __init txx9_clocksource_init(unsigned long baseaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned int imbusclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct txx9_tmr_reg __iomem *tmrptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) clocksource_register_hz(&txx9_clocksource.cs, TIMER_CLK(imbusclk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) __raw_writel(TCR_BASE, &tmrptr->tcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) __raw_writel(0, &tmrptr->tisr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) __raw_writel(TIMER_CCD, &tmrptr->ccdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __raw_writel(TXx9_TMITMR_TZCE, &tmrptr->itmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) __raw_writel(1 << TXX9_CLOCKSOURCE_BITS, &tmrptr->cpra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) txx9_clocksource.tmrptr = tmrptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) sched_clock_register(txx9_read_sched_clock, TXX9_CLOCKSOURCE_BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) TIMER_CLK(imbusclk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct txx9_clock_event_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct clock_event_device cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct txx9_tmr_reg __iomem *tmrptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static void txx9tmr_stop_and_clear(struct txx9_tmr_reg __iomem *tmrptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* stop and reset counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __raw_writel(TCR_BASE, &tmrptr->tcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* clear pending interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) __raw_writel(0, &tmrptr->tisr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int txx9tmr_set_state_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct txx9_clock_event_device *txx9_cd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) container_of(evt, struct txx9_clock_event_device, cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) txx9tmr_stop_and_clear(tmrptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) __raw_writel(TXx9_TMITMR_TIIE | TXx9_TMITMR_TZCE, &tmrptr->itmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* start timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) __raw_writel(((u64)(NSEC_PER_SEC / HZ) * evt->mult) >> evt->shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) &tmrptr->cpra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int txx9tmr_set_state_oneshot(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct txx9_clock_event_device *txx9_cd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) container_of(evt, struct txx9_clock_event_device, cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) txx9tmr_stop_and_clear(tmrptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) __raw_writel(TXx9_TMITMR_TIIE, &tmrptr->itmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int txx9tmr_set_state_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct txx9_clock_event_device *txx9_cd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) container_of(evt, struct txx9_clock_event_device, cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) txx9tmr_stop_and_clear(tmrptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) __raw_writel(0, &tmrptr->itmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int txx9tmr_tick_resume(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct txx9_clock_event_device *txx9_cd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) container_of(evt, struct txx9_clock_event_device, cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) txx9tmr_stop_and_clear(tmrptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) __raw_writel(TIMER_CCD, &tmrptr->ccdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) __raw_writel(0, &tmrptr->itmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int txx9tmr_set_next_event(unsigned long delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct txx9_clock_event_device *txx9_cd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) container_of(evt, struct txx9_clock_event_device, cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) txx9tmr_stop_and_clear(tmrptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* start timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) __raw_writel(delta, &tmrptr->cpra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static struct txx9_clock_event_device txx9_clock_event_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .cd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .name = "TXx9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .features = CLOCK_EVT_FEAT_PERIODIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) CLOCK_EVT_FEAT_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .rating = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .set_state_shutdown = txx9tmr_set_state_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .set_state_periodic = txx9tmr_set_state_periodic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .set_state_oneshot = txx9tmr_set_state_oneshot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .tick_resume = txx9tmr_tick_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .set_next_event = txx9tmr_set_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static irqreturn_t txx9tmr_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct txx9_clock_event_device *txx9_cd = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct clock_event_device *cd = &txx9_cd->cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) __raw_writel(0, &tmrptr->tisr); /* ack interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) cd->event_handler(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) void __init txx9_clockevent_init(unsigned long baseaddr, int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned int imbusclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct clock_event_device *cd = &txx9_clock_event_device.cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct txx9_tmr_reg __iomem *tmrptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) txx9tmr_stop_and_clear(tmrptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) __raw_writel(TIMER_CCD, &tmrptr->ccdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) __raw_writel(0, &tmrptr->itmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) txx9_clock_event_device.tmrptr = tmrptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) clockevent_set_clock(cd, TIMER_CLK(imbusclk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) cd->max_delta_ns =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) clockevent_delta2ns(0xffffffff >> (32 - TXX9_TIMER_BITS), cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) cd->max_delta_ticks = 0xffffffff >> (32 - TXX9_TIMER_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) cd->min_delta_ns = clockevent_delta2ns(0xf, cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) cd->min_delta_ticks = 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) cd->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) cd->cpumask = cpumask_of(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) clockevents_register_device(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (request_irq(irq, txx9tmr_interrupt, IRQF_PERCPU | IRQF_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "txx9tmr", &txx9_clock_event_device))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) pr_err("Failed to request irq %d (txx9tmr)\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) printk(KERN_INFO "TXx9: clockevent device at 0x%lx, irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) baseaddr, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) void __init txx9_tmr_init(unsigned long baseaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct txx9_tmr_reg __iomem *tmrptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Start once to make CounterResetEnable effective */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) __raw_writel(TXx9_TMTCR_CRE | TXx9_TMTCR_TCE, &tmrptr->tcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Stop and reset the counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) __raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) __raw_writel(0, &tmrptr->tisr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) __raw_writel(0xffffffff, &tmrptr->cpra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) __raw_writel(0, &tmrptr->itmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) __raw_writel(0, &tmrptr->ccdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) __raw_writel(0, &tmrptr->pgmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) iounmap(tmrptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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