^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2000, 2001 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/percpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/addrspace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/sibyte/sb1250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/sibyte/sb1250_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/sibyte/sb1250_int.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/sibyte/sb1250_scd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IMR_IP2_VAL K_INT_MAP_I0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IMR_IP3_VAL K_INT_MAP_I1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IMR_IP4_VAL K_INT_MAP_I2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * The general purpose timer ticks at 1MHz independent if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * the rest of the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static int sibyte_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) void __iomem *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) cfg = IOADDR(A_SCD_TIMER_REGISTER(smp_processor_id(), R_SCD_TIMER_CFG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Stop the timer until we actually program a shot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) __raw_writeq(0, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static int sibyte_set_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) void __iomem *cfg, *init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) __raw_writeq(0, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) void __iomem *cfg, *init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) __raw_writeq(0, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) __raw_writeq(delta - 1, init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __raw_writeq(M_SCD_TIMER_ENABLE, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct clock_event_device *cd = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) void __iomem *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned long tmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (clockevent_state_periodic(cd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) tmode = M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) tmode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* ACK interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ____raw_writeq(tmode, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) cd->event_handler(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static DEFINE_PER_CPU(char [18], sibyte_hpt_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) void sb1250_clockevent_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int irq = K_INT_TIMER_0 + cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned char *name = per_cpu(sibyte_hpt_name, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned long flags = IRQF_PERCPU | IRQF_TIMER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Only have 4 general purpose timers, and we use last one as hpt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) BUG_ON(cpu > 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) sprintf(name, "sb1250-counter-%d", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) cd->name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) cd->features = CLOCK_EVT_FEAT_PERIODIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) CLOCK_EVT_FEAT_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) clockevent_set_clock(cd, V_SCD_TIMER_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) cd->max_delta_ns = clockevent_delta2ns(0x7fffff, cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) cd->max_delta_ticks = 0x7fffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) cd->min_delta_ns = clockevent_delta2ns(2, cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) cd->min_delta_ticks = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) cd->rating = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) cd->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) cd->cpumask = cpumask_of(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) cd->set_next_event = sibyte_next_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) cd->set_state_shutdown = sibyte_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) cd->set_state_periodic = sibyte_set_periodic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) cd->set_state_oneshot = sibyte_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) clockevents_register_device(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) sb1250_mask_irq(cpu, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * Map the timer interrupt to IP[4] of this cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) __raw_writeq(IMR_IP4_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) (irq << 3)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) sb1250_unmask_irq(cpu, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) irq_set_affinity(irq, cpumask_of(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (request_irq(irq, sibyte_counter_handler, flags, name, cd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) pr_err("Failed to request irq %d (%s)\n", irq, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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