Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2007 MIPS Technologies, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/percpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/cevt-r4k.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) static int mips_next_event(unsigned long delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 			   struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	unsigned int cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	cnt = read_c0_count();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	cnt += delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	write_c0_compare(cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	res = ((int)(read_c0_count() - cnt) >= 0) ? -ETIME : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * calculate_min_delta() - Calculate a good minimum delta for mips_next_event().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * Running under virtualisation can introduce overhead into mips_next_event() in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * the form of hypervisor emulation of CP0_Count/CP0_Compare registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * potentially with an unnatural frequency, which makes a fixed min_delta_ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * value inappropriate as it may be too small.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * It can also introduce occasional latency from the guest being descheduled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * This function calculates a good minimum delta based roughly on the 75th
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * percentile of the time taken to do the mips_next_event() sequence, in order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * to handle potentially higher overhead while also eliminating outliers due to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * unpredictable hypervisor latency (which can be handled by retries).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  * Return:	An appropriate minimum delta for the clock event device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static unsigned int calculate_min_delta(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	unsigned int cnt, i, j, k, l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	unsigned int buf1[4], buf2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	unsigned int min_delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	 * Calculate the median of 5 75th percentiles of 5 samples of how long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	 * it takes to set CP0_Compare = CP0_Count + delta.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	for (i = 0; i < 5; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		for (j = 0; j < 5; ++j) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 			 * This is like the code in mips_next_event(), and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 			 * directly measures the borderline "safe" delta.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 			cnt = read_c0_count();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 			write_c0_compare(cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 			cnt = read_c0_count() - cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 			/* Sorted insert into buf1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 			for (k = 0; k < j; ++k) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 				if (cnt < buf1[k]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 					l = min_t(unsigned int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 						  j, ARRAY_SIZE(buf1) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 					for (; l > k; --l)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 						buf1[l] = buf1[l - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 					break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 				}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 			if (k < ARRAY_SIZE(buf1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 				buf1[k] = cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		/* Sorted insert of 75th percentile into buf2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		for (k = 0; k < i && k < ARRAY_SIZE(buf2); ++k) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 			if (buf1[ARRAY_SIZE(buf1) - 1] < buf2[k]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 				l = min_t(unsigned int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 					  i, ARRAY_SIZE(buf2) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 				for (; l > k; --l)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 					buf2[l] = buf2[l - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		if (k < ARRAY_SIZE(buf2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 			buf2[k] = buf1[ARRAY_SIZE(buf1) - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	/* Use 2 * median of 75th percentiles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	min_delta = buf2[ARRAY_SIZE(buf2) - 1] * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	/* Don't go too low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	if (min_delta < 0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		min_delta = 0x300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	pr_debug("%s: median 75th percentile=%#x, min_delta=%#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		 __func__, buf2[ARRAY_SIZE(buf2) - 1], min_delta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	return min_delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int cp0_timer_irq_installed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)  * Possibly handle a performance counter interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)  * Return true if the timer interrupt should not be checked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static inline int handle_perf_irq(int r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	 * The performance counter overflow interrupt may be shared with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	 * timer interrupt (cp0_perfcount_irq < 0). If it is and a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	 * performance counter has overflowed (perf_irq() == IRQ_HANDLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	 * and we can't reliably determine if a counter interrupt has also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	 * happened (!r2) then don't check for a timer interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	return (cp0_perfcount_irq < 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		perf_irq() == IRQ_HANDLED &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		!r2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	const int r2 = cpu_has_mips_r2_r6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	struct clock_event_device *cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	 * Suckage alert:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	 * Before R2 of the architecture there was no way to see if a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	 * performance counter interrupt was pending, so we have to run
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	 * the performance counter interrupt handler anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	if (handle_perf_irq(r2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	 * The same applies to performance counter interrupts.	But with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	 * above we now know that the reason we got here must be a timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	 * interrupt.  Being the paranoiacs we are we check anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	if (!r2 || (read_c0_cause() & CAUSEF_TI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		/* Clear Count/Compare Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		write_c0_compare(read_c0_compare());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		cd = &per_cpu(mips_clockevent_device, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		cd->event_handler(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct irqaction c0_compare_irqaction = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	.handler = c0_compare_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	 * IRQF_SHARED: The timer interrupt may be shared with other interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	 * such as perf counter and FDC interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	.flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.name = "timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) void mips_event_handler(struct clock_event_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)  * FIXME: This doesn't hold for the relocated E9000 compare interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int c0_compare_int_pending(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	/* When cpu_has_mips_r2, this checks Cause.TI instead of Cause.IP7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)  * Compare interrupt can be routed and latched outside the core,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)  * so wait up to worst case number of cycle counter ticks for timer interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)  * changes to propagate to the cause register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define COMPARE_INT_SEEN_TICKS 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int c0_compare_int_usable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	unsigned int delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	unsigned int cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #ifdef CONFIG_KVM_GUEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)     return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	 * IP7 already pending?	 Try to clear it by acking the timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	if (c0_compare_int_pending()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		cnt = read_c0_count();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		write_c0_compare(cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		back_to_back_c0_hazard();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		while (read_c0_count() < (cnt  + COMPARE_INT_SEEN_TICKS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			if (!c0_compare_int_pending())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		if (c0_compare_int_pending())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	for (delta = 0x10; delta <= 0x400000; delta <<= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		cnt = read_c0_count();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		cnt += delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		write_c0_compare(cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		back_to_back_c0_hazard();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		if ((int)(read_c0_count() - cnt) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		    break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		/* increase delta if the timer was already expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	while ((int)(read_c0_count() - cnt) <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		;	/* Wait for expiry  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		if (c0_compare_int_pending())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	if (!c0_compare_int_pending())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	cnt = read_c0_count();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	write_c0_compare(cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	back_to_back_c0_hazard();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		if (!c0_compare_int_pending())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	if (c0_compare_int_pending())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	 * Feels like a real count / compare timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned int __weak get_c0_compare_int(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	return MIPS_CPU_IRQ_BASE + cp0_compare_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #ifdef CONFIG_CPU_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static unsigned long mips_ref_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int r4k_cpufreq_callback(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 				unsigned long val, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	struct cpufreq_freqs *freq = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	struct clock_event_device *cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	if (!mips_ref_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		mips_ref_freq = freq->old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	if (val == CPUFREQ_POSTCHANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		rate = cpufreq_scale(mips_hpt_frequency, mips_ref_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 				     freq->new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		for_each_cpu(cpu, freq->policy->cpus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			cd = &per_cpu(mips_clockevent_device, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 			clockevents_update_freq(cd, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static struct notifier_block r4k_cpufreq_notifier = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	.notifier_call  = r4k_cpufreq_callback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int __init r4k_register_cpufreq_notifier(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	return cpufreq_register_notifier(&r4k_cpufreq_notifier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 					 CPUFREQ_TRANSITION_NOTIFIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) core_initcall(r4k_register_cpufreq_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #endif /* !CONFIG_CPU_FREQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int r4k_clockevent_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	unsigned long flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	unsigned int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	struct clock_event_device *cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	unsigned int irq, min_delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	if (!cpu_has_counter || !mips_hpt_frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	if (!c0_compare_int_usable())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	 * With vectored interrupts things are getting platform specific.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	 * get_c0_compare_int is a hook to allow a platform to return the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	 * interrupt number of its liking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	irq = get_c0_compare_int();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	cd = &per_cpu(mips_clockevent_device, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	cd->name		= "MIPS";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	cd->features		= CLOCK_EVT_FEAT_ONESHOT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 				  CLOCK_EVT_FEAT_C3STOP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 				  CLOCK_EVT_FEAT_PERCPU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	min_delta		= calculate_min_delta();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	cd->rating		= 300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	cd->irq			= irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	cd->cpumask		= cpumask_of(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	cd->set_next_event	= mips_next_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	cd->event_handler	= mips_event_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	clockevents_config_and_register(cd, mips_hpt_frequency, min_delta, 0x7fffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	if (cp0_timer_irq_installed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	cp0_timer_irq_installed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	if (request_irq(irq, c0_compare_interrupt, flags, "timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 			c0_compare_interrupt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		pr_err("Failed to request irq %d (timer)\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)