^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * GT641xx clockevent routines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/gt64120.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static DEFINE_RAW_SPINLOCK(gt641xx_timer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static unsigned int gt641xx_base_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) void gt641xx_set_base_clock(unsigned int clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) gt641xx_base_clock = clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) int gt641xx_timer0_state(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) if (GT_READ(GT_TC0_OFS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) GT_WRITE(GT_TC0_OFS, gt641xx_base_clock / HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static int gt641xx_timer0_set_next_event(unsigned long delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) raw_spin_lock(>641xx_timer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ctrl = GT_READ(GT_TC_CONTROL_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ctrl |= GT_TC_CONTROL_ENTC0_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) GT_WRITE(GT_TC0_OFS, delta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) GT_WRITE(GT_TC_CONTROL_OFS, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) raw_spin_unlock(>641xx_timer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static int gt641xx_timer0_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) raw_spin_lock(>641xx_timer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ctrl = GT_READ(GT_TC_CONTROL_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) GT_WRITE(GT_TC_CONTROL_OFS, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) raw_spin_unlock(>641xx_timer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int gt641xx_timer0_set_oneshot(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) raw_spin_lock(>641xx_timer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ctrl = GT_READ(GT_TC_CONTROL_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ctrl &= ~GT_TC_CONTROL_SELTC0_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ctrl |= GT_TC_CONTROL_ENTC0_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) GT_WRITE(GT_TC_CONTROL_OFS, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) raw_spin_unlock(>641xx_timer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static int gt641xx_timer0_set_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) raw_spin_lock(>641xx_timer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ctrl = GT_READ(GT_TC_CONTROL_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ctrl |= GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) GT_WRITE(GT_TC_CONTROL_OFS, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) raw_spin_unlock(>641xx_timer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static void gt641xx_timer0_event_handler(struct clock_event_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static struct clock_event_device gt641xx_timer0_clockevent = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .name = "gt641xx-timer0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .features = CLOCK_EVT_FEAT_PERIODIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) CLOCK_EVT_FEAT_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .irq = GT641XX_TIMER0_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .set_next_event = gt641xx_timer0_set_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .set_state_shutdown = gt641xx_timer0_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .set_state_periodic = gt641xx_timer0_set_periodic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .set_state_oneshot = gt641xx_timer0_set_oneshot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .tick_resume = gt641xx_timer0_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .event_handler = gt641xx_timer0_event_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static irqreturn_t gt641xx_timer0_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct clock_event_device *cd = >641xx_timer0_clockevent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) cd->event_handler(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int __init gt641xx_timer0_clockevent_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct clock_event_device *cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (!gt641xx_base_clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) GT_WRITE(GT_TC0_OFS, gt641xx_base_clock / HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) cd = >641xx_timer0_clockevent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) cd->rating = 200 + gt641xx_base_clock / 10000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) clockevent_set_clock(cd, gt641xx_base_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) cd->max_delta_ticks = 0x7fffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) cd->min_delta_ticks = 0x300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) cd->cpumask = cpumask_of(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) clockevents_register_device(>641xx_timer0_clockevent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return request_irq(GT641XX_TIMER0_IRQ, gt641xx_timer0_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) IRQF_PERCPU | IRQF_TIMER, "gt641xx_timer0", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) arch_initcall(gt641xx_timer0_clockevent_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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