^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1996, 97, 2000, 2001 by Ralf Baechle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2001 MIPS Technologies, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/sched/signal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/signal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/branch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/cpu-features.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/fpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/fpu_emulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/inst.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/mips-r2-to-r6-emul.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "probes-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Calculate and return exception PC in case of branch delay slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * for microMIPS and MIPS16e. It does not clear the ISA mode bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) int __isa_exception_epc(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned short inst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) long epc = regs->cp0_epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Calculate exception PC in branch delay slot. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (__get_user(inst, (u16 __user *) msk_isa16_mode(epc))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* This should never happen because delay slot was checked. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) force_sig(SIGSEGV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) return epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) if (cpu_has_mips16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) union mips16e_instruction inst_mips16e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) inst_mips16e.full = inst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (inst_mips16e.ri.opcode == MIPS16e_jal_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) epc += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) epc += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) } else if (mm_insn_16bit(inst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) epc += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) epc += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int __mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned long *contpc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) union mips_instruction insn = (union mips_instruction)dec_insn.insn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int __maybe_unused bc_false = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (!cpu_has_mmips)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) switch (insn.mm_i_format.opcode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) case mm_pool32a_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) mm_pool32axf_op) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) switch (insn.mm_i_format.simmediate >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MM_POOL32A_MINOR_SHIFT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) case mm_jalr_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) case mm_jalrhb_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) case mm_jalrs_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) case mm_jalrshb_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (insn.mm_i_format.rt != 0) /* Not mm_jr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) regs->regs[insn.mm_i_format.rt] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) regs->cp0_epc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) dec_insn.pc_inc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) dec_insn.next_pc_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) *contpc = regs->regs[insn.mm_i_format.rs];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) case mm_pool32i_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) switch (insn.mm_i_format.rt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) case mm_bltzals_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) case mm_bltzal_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) regs->regs[31] = regs->cp0_epc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) dec_insn.pc_inc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) dec_insn.next_pc_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) case mm_bltz_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if ((long)regs->regs[insn.mm_i_format.rs] < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) *contpc = regs->cp0_epc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) dec_insn.pc_inc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) (insn.mm_i_format.simmediate << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) *contpc = regs->cp0_epc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) dec_insn.pc_inc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) dec_insn.next_pc_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) case mm_bgezals_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) case mm_bgezal_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) regs->regs[31] = regs->cp0_epc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) dec_insn.pc_inc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) dec_insn.next_pc_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) case mm_bgez_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if ((long)regs->regs[insn.mm_i_format.rs] >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) *contpc = regs->cp0_epc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) dec_insn.pc_inc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) (insn.mm_i_format.simmediate << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) *contpc = regs->cp0_epc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) dec_insn.pc_inc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) dec_insn.next_pc_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case mm_blez_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) *contpc = regs->cp0_epc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) dec_insn.pc_inc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) (insn.mm_i_format.simmediate << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) *contpc = regs->cp0_epc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) dec_insn.pc_inc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) dec_insn.next_pc_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) case mm_bgtz_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) *contpc = regs->cp0_epc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) dec_insn.pc_inc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) (insn.mm_i_format.simmediate << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) *contpc = regs->cp0_epc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) dec_insn.pc_inc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) dec_insn.next_pc_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #ifdef CONFIG_MIPS_FP_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) case mm_bc2f_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) case mm_bc1f_op: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned int fcr31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) bc_false = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) case mm_bc2t_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) case mm_bc1t_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (is_fpu_owner())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) fcr31 = read_32bit_cp1_register(CP1_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) fcr31 = current->thread.fpu.fcr31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (bc_false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) fcr31 = ~fcr31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) bit = (insn.mm_i_format.rs >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) bit += (bit != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) bit += 23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (fcr31 & (1 << bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) *contpc = regs->cp0_epc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dec_insn.pc_inc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) (insn.mm_i_format.simmediate << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) *contpc = regs->cp0_epc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) dec_insn.pc_inc + dec_insn.next_pc_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #endif /* CONFIG_MIPS_FP_SUPPORT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) case mm_pool16c_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) switch (insn.mm_i_format.rt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) case mm_jalr16_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) case mm_jalrs16_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) regs->regs[31] = regs->cp0_epc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) dec_insn.pc_inc + dec_insn.next_pc_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) case mm_jr16_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) *contpc = regs->regs[insn.mm_i_format.rs];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) case mm_beqz16_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) *contpc = regs->cp0_epc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) dec_insn.pc_inc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) (insn.mm_b1_format.simmediate << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) *contpc = regs->cp0_epc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) dec_insn.pc_inc + dec_insn.next_pc_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) case mm_bnez16_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) *contpc = regs->cp0_epc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dec_insn.pc_inc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) (insn.mm_b1_format.simmediate << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) *contpc = regs->cp0_epc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dec_insn.pc_inc + dec_insn.next_pc_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) case mm_b16_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) *contpc = regs->cp0_epc + dec_insn.pc_inc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) (insn.mm_b0_format.simmediate << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) case mm_beq32_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (regs->regs[insn.mm_i_format.rs] ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) regs->regs[insn.mm_i_format.rt])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) *contpc = regs->cp0_epc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) dec_insn.pc_inc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) (insn.mm_i_format.simmediate << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) *contpc = regs->cp0_epc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) dec_insn.pc_inc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dec_insn.next_pc_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) case mm_bne32_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (regs->regs[insn.mm_i_format.rs] !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) regs->regs[insn.mm_i_format.rt])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) *contpc = regs->cp0_epc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dec_insn.pc_inc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) (insn.mm_i_format.simmediate << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) *contpc = regs->cp0_epc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dec_insn.pc_inc + dec_insn.next_pc_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) case mm_jalx32_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) regs->regs[31] = regs->cp0_epc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) dec_insn.pc_inc + dec_insn.next_pc_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) *contpc = regs->cp0_epc + dec_insn.pc_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) *contpc >>= 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) *contpc <<= 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) *contpc |= (insn.j_format.target << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) case mm_jals32_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) case mm_jal32_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) regs->regs[31] = regs->cp0_epc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) dec_insn.pc_inc + dec_insn.next_pc_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case mm_j32_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) *contpc = regs->cp0_epc + dec_insn.pc_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) *contpc >>= 27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) *contpc <<= 27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) *contpc |= (insn.j_format.target << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) set_isa16_mode(*contpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * Compute return address and emulate branch in microMIPS mode after an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * exception only. It does not handle compact branches/jumps and cannot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * be used in interrupt context. (Compact branches/jumps do not cause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * exceptions.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int __microMIPS_compute_return_epc(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u16 __user *pc16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u16 halfword;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned int word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned long contpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct mm_decoded_insn mminsn = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) mminsn.micro_mips_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* This load never faults. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) pc16 = (unsigned short __user *)msk_isa16_mode(regs->cp0_epc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) __get_user(halfword, pc16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) pc16++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) contpc = regs->cp0_epc + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) word = ((unsigned int)halfword << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) mminsn.pc_inc = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (!mm_insn_16bit(halfword)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) __get_user(halfword, pc16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) pc16++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) contpc = regs->cp0_epc + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) mminsn.pc_inc = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) word |= halfword;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) mminsn.insn = word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (get_user(halfword, pc16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) goto sigsegv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) mminsn.next_pc_inc = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) word = ((unsigned int)halfword << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (!mm_insn_16bit(halfword)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) pc16++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (get_user(halfword, pc16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) goto sigsegv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) mminsn.next_pc_inc = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) word |= halfword;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) mminsn.next_insn = word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) mm_isBranchInstr(regs, mminsn, &contpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) regs->cp0_epc = contpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) sigsegv:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) force_sig(SIGSEGV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * Compute return address and emulate branch in MIPS16e mode after an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * exception only. It does not handle compact branches/jumps and cannot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * be used in interrupt context. (Compact branches/jumps do not cause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * exceptions.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int __MIPS16e_compute_return_epc(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u16 __user *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) union mips16e_instruction inst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u16 inst2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u32 fullinst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) long epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) epc = regs->cp0_epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* Read the instruction. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) addr = (u16 __user *)msk_isa16_mode(epc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (__get_user(inst.full, addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) force_sig(SIGSEGV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) switch (inst.ri.opcode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) case MIPS16e_extend_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) regs->cp0_epc += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * JAL and JALX in MIPS16e mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) case MIPS16e_jal_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) addr += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (__get_user(inst2, addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) force_sig(SIGSEGV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) fullinst = ((unsigned)inst.full << 16) | inst2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) regs->regs[31] = epc + 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) epc += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) epc >>= 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) epc <<= 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * JAL:5 X:1 TARGET[20-16]:5 TARGET[25:21]:5 TARGET[15:0]:16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * ......TARGET[15:0].................TARGET[20:16]...........
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * ......TARGET[25:21]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) epc |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ((fullinst & 0xffff) << 2) | ((fullinst & 0x3e00000) >> 3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ((fullinst & 0x1f0000) << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (!inst.jal.x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) set_isa16_mode(epc); /* Set ISA mode bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) regs->cp0_epc = epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * J(AL)R(C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) case MIPS16e_rr_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (inst.rr.func == MIPS16e_jr_func) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (inst.rr.ra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) regs->cp0_epc = regs->regs[31];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) regs->cp0_epc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) regs->regs[reg16to32[inst.rr.rx]];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (inst.rr.l) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (inst.rr.nd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) regs->regs[31] = epc + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) regs->regs[31] = epc + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * All other cases have no branch delay slot and are 16-bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * Branches do not cause an exception.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) regs->cp0_epc += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * __compute_return_epc_for_insn - Computes the return address and do emulate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * branch simulation, if required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * @regs: Pointer to pt_regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * @insn: branch instruction to decode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * Return: -EFAULT on error and forces SIGILL, and on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * returns 0 or BRANCH_LIKELY_TAKEN as appropriate after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * evaluating the branch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * MIPS R6 Compact branches and forbidden slots:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * Compact branches do not throw exceptions because they do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * not have delay slots. The forbidden slot instruction ($PC+4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * is only executed if the branch was not taken. Otherwise the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * forbidden slot is skipped entirely. This means that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * only possible reason to be here because of a MIPS R6 compact
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * branch instruction is that the forbidden slot has thrown one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * In that case the branch was not taken, so the EPC can be safely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * set to EPC + 8.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int __compute_return_epc_for_insn(struct pt_regs *regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) union mips_instruction insn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) long epc = regs->cp0_epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) unsigned int dspcontrol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) switch (insn.i_format.opcode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * jr and jalr are in r_format format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) case spec_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) switch (insn.r_format.func) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) case jalr_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) regs->regs[insn.r_format.rd] = epc + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) case jr_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (NO_R6EMU && insn.r_format.func == jr_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) goto sigill_r2r6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) regs->cp0_epc = regs->regs[insn.r_format.rs];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * This group contains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * bltz_op, bgez_op, bltzl_op, bgezl_op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) case bcond_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) switch (insn.i_format.rt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) case bltzl_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (NO_R6EMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) goto sigill_r2r6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) case bltz_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if ((long)regs->regs[insn.i_format.rs] < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) epc = epc + 4 + (insn.i_format.simmediate << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (insn.i_format.rt == bltzl_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ret = BRANCH_LIKELY_TAKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) epc += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) regs->cp0_epc = epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) case bgezl_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (NO_R6EMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) goto sigill_r2r6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) case bgez_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if ((long)regs->regs[insn.i_format.rs] >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) epc = epc + 4 + (insn.i_format.simmediate << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (insn.i_format.rt == bgezl_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ret = BRANCH_LIKELY_TAKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) epc += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) regs->cp0_epc = epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) case bltzal_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) case bltzall_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (NO_R6EMU && (insn.i_format.rs ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) insn.i_format.rt == bltzall_op))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) goto sigill_r2r6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) regs->regs[31] = epc + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * OK we are here either because we hit a NAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * instruction or because we are emulating an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * old bltzal{,l} one. Let's figure out what the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * case really is.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (!insn.i_format.rs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * NAL or BLTZAL with rs == 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * Doesn't matter if we are R6 or not. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * result is the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) regs->cp0_epc += 4 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) (insn.i_format.simmediate << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* Now do the real thing for non-R6 BLTZAL{,L} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if ((long)regs->regs[insn.i_format.rs] < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) epc = epc + 4 + (insn.i_format.simmediate << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (insn.i_format.rt == bltzall_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ret = BRANCH_LIKELY_TAKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) epc += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) regs->cp0_epc = epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) case bgezal_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) case bgezall_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (NO_R6EMU && (insn.i_format.rs ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) insn.i_format.rt == bgezall_op))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) goto sigill_r2r6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) regs->regs[31] = epc + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * OK we are here either because we hit a BAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * instruction or because we are emulating an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * old bgezal{,l} one. Let's figure out what the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * case really is.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (!insn.i_format.rs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * BAL or BGEZAL with rs == 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * Doesn't matter if we are R6 or not. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * result is the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) regs->cp0_epc += 4 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) (insn.i_format.simmediate << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* Now do the real thing for non-R6 BGEZAL{,L} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if ((long)regs->regs[insn.i_format.rs] >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) epc = epc + 4 + (insn.i_format.simmediate << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (insn.i_format.rt == bgezall_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ret = BRANCH_LIKELY_TAKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) epc += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) regs->cp0_epc = epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) case bposge32_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (!cpu_has_dsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) goto sigill_dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) dspcontrol = rddsp(0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (dspcontrol >= 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) epc = epc + 4 + (insn.i_format.simmediate << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) epc += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) regs->cp0_epc = epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * These are unconditional and in j_format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) case jalx_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) case jal_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) regs->regs[31] = regs->cp0_epc + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) case j_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) epc += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) epc >>= 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) epc <<= 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) epc |= (insn.j_format.target << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) regs->cp0_epc = epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (insn.i_format.opcode == jalx_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) set_isa16_mode(regs->cp0_epc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * These are conditional and in i_format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) case beql_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (NO_R6EMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) goto sigill_r2r6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) case beq_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (regs->regs[insn.i_format.rs] ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) regs->regs[insn.i_format.rt]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) epc = epc + 4 + (insn.i_format.simmediate << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (insn.i_format.opcode == beql_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ret = BRANCH_LIKELY_TAKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) epc += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) regs->cp0_epc = epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) case bnel_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (NO_R6EMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) goto sigill_r2r6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) case bne_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (regs->regs[insn.i_format.rs] !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) regs->regs[insn.i_format.rt]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) epc = epc + 4 + (insn.i_format.simmediate << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (insn.i_format.opcode == bnel_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ret = BRANCH_LIKELY_TAKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) epc += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) regs->cp0_epc = epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) case blezl_op: /* not really i_format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (!insn.i_format.rt && NO_R6EMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) goto sigill_r2r6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) case blez_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * Compact branches for R6 for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * blez and blezl opcodes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * BLEZ | rs = 0 | rt != 0 == BLEZALC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * BLEZ | rs = rt != 0 == BGEZALC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * BLEZ | rs != 0 | rt != 0 == BGEUC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * BLEZL | rs = 0 | rt != 0 == BLEZC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * BLEZL | rs = rt != 0 == BGEZC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * BLEZL | rs != 0 | rt != 0 == BGEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * For real BLEZ{,L}, rt is always 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (cpu_has_mips_r6 && insn.i_format.rt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if ((insn.i_format.opcode == blez_op) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) ((!insn.i_format.rs && insn.i_format.rt) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) (insn.i_format.rs == insn.i_format.rt)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) regs->regs[31] = epc + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) regs->cp0_epc += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* rt field assumed to be zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if ((long)regs->regs[insn.i_format.rs] <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) epc = epc + 4 + (insn.i_format.simmediate << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (insn.i_format.opcode == blezl_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ret = BRANCH_LIKELY_TAKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) epc += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) regs->cp0_epc = epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) case bgtzl_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (!insn.i_format.rt && NO_R6EMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) goto sigill_r2r6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) case bgtz_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * Compact branches for R6 for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * bgtz and bgtzl opcodes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * BGTZ | rs = 0 | rt != 0 == BGTZALC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * BGTZ | rs = rt != 0 == BLTZALC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * BGTZ | rs != 0 | rt != 0 == BLTUC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * BGTZL | rs = 0 | rt != 0 == BGTZC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * BGTZL | rs = rt != 0 == BLTZC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * BGTZL | rs != 0 | rt != 0 == BLTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * *ZALC varint for BGTZ &&& rt != 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * For real GTZ{,L}, rt is always 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (cpu_has_mips_r6 && insn.i_format.rt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if ((insn.i_format.opcode == blez_op) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ((!insn.i_format.rs && insn.i_format.rt) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) (insn.i_format.rs == insn.i_format.rt)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) regs->regs[31] = epc + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) regs->cp0_epc += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* rt field assumed to be zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if ((long)regs->regs[insn.i_format.rs] > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) epc = epc + 4 + (insn.i_format.simmediate << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (insn.i_format.opcode == bgtzl_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ret = BRANCH_LIKELY_TAKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) epc += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) regs->cp0_epc = epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #ifdef CONFIG_MIPS_FP_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * And now the FPA/cp1 branch instructions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) case cop1_op: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) unsigned int bit, fcr31, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (cpu_has_mips_r6 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ((insn.i_format.rs == bc1eqz_op) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) (insn.i_format.rs == bc1nez_op))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (!init_fp_ctx(current))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) lose_fpu(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) reg = insn.i_format.rt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) bit = get_fpr32(¤t->thread.fpu.fpr[reg], 0) & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (insn.i_format.rs == bc1eqz_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) bit = !bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) own_fpu(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) epc = epc + 4 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) (insn.i_format.simmediate << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) epc += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) regs->cp0_epc = epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (is_fpu_owner())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) fcr31 = read_32bit_cp1_register(CP1_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) fcr31 = current->thread.fpu.fcr31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) bit = (insn.i_format.rt >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) bit += (bit != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) bit += 23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) switch (insn.i_format.rt & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) case 0: /* bc1f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) case 2: /* bc1fl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (~fcr31 & (1 << bit)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) epc = epc + 4 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) (insn.i_format.simmediate << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (insn.i_format.rt == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) ret = BRANCH_LIKELY_TAKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) epc += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) regs->cp0_epc = epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) case 1: /* bc1t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) case 3: /* bc1tl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (fcr31 & (1 << bit)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) epc = epc + 4 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) (insn.i_format.simmediate << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (insn.i_format.rt == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) ret = BRANCH_LIKELY_TAKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) epc += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) regs->cp0_epc = epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #endif /* CONFIG_MIPS_FP_SUPPORT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #ifdef CONFIG_CPU_CAVIUM_OCTEON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) case lwc2_op: /* This is bbit0 on Octeon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) epc = epc + 4 + (insn.i_format.simmediate << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) epc += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) regs->cp0_epc = epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) case ldc2_op: /* This is bbit032 on Octeon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if ((regs->regs[insn.i_format.rs] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) (1ull<<(insn.i_format.rt+32))) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) epc = epc + 4 + (insn.i_format.simmediate << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) epc += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) regs->cp0_epc = epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) case swc2_op: /* This is bbit1 on Octeon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) epc = epc + 4 + (insn.i_format.simmediate << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) epc += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) regs->cp0_epc = epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) case sdc2_op: /* This is bbit132 on Octeon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (regs->regs[insn.i_format.rs] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) (1ull<<(insn.i_format.rt+32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) epc = epc + 4 + (insn.i_format.simmediate << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) epc += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) regs->cp0_epc = epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) case bc6_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* Only valid for MIPS R6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (!cpu_has_mips_r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) goto sigill_r6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) regs->cp0_epc += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) case balc6_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (!cpu_has_mips_r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) goto sigill_r6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /* Compact branch: BALC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) regs->regs[31] = epc + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) epc += 4 + (insn.i_format.simmediate << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) regs->cp0_epc = epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) case pop66_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (!cpu_has_mips_r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) goto sigill_r6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /* Compact branch: BEQZC || JIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) regs->cp0_epc += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) case pop76_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (!cpu_has_mips_r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) goto sigill_r6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /* Compact branch: BNEZC || JIALC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (!insn.i_format.rs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /* JIALC: set $31/ra */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) regs->regs[31] = epc + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) regs->cp0_epc += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) case pop10_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) case pop30_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /* Only valid for MIPS R6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (!cpu_has_mips_r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) goto sigill_r6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * Compact branches:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) * bovc, beqc, beqzalc, bnvc, bnec, bnezlac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (insn.i_format.rt && !insn.i_format.rs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) regs->regs[31] = epc + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) regs->cp0_epc += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) sigill_dsp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) pr_debug("%s: DSP branch but not DSP ASE - sending SIGILL.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) current->comm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) force_sig(SIGILL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) sigill_r2r6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) pr_debug("%s: R2 branch but r2-to-r6 emulator is not present - sending SIGILL.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) current->comm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) force_sig(SIGILL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) sigill_r6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) pr_debug("%s: R6 branch but no MIPSr6 ISA support - sending SIGILL.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) current->comm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) force_sig(SIGILL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) EXPORT_SYMBOL_GPL(__compute_return_epc_for_insn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) int __compute_return_epc(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) unsigned int __user *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) long epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) union mips_instruction insn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) epc = regs->cp0_epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (epc & 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) goto unaligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) * Read the instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) addr = (unsigned int __user *) epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (__get_user(insn.word, addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) force_sig(SIGSEGV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return __compute_return_epc_for_insn(regs, insn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) unaligned:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) printk("%s: unaligned epc - sending SIGBUS.\n", current->comm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) force_sig(SIGBUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #if (defined CONFIG_KPROBES) || (defined CONFIG_UPROBES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) int __insn_is_compact_branch(union mips_instruction insn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (!cpu_has_mips_r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) switch (insn.i_format.opcode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) case blezl_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) case bgtzl_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) case blez_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) case bgtz_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) * blez[l] and bgtz[l] opcodes with non-zero rt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) * are MIPS R6 compact branches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (insn.i_format.rt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) case bc6_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) case balc6_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) case pop10_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) case pop30_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) case pop66_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) case pop76_op:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) EXPORT_SYMBOL_GPL(__insn_is_compact_branch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #endif /* CONFIG_KPROBES || CONFIG_UPROBES */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags