Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Reset/NMI/re-entry vectors for BMIPS processors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm/asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/asmmacro.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/cacheops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/regdef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/stackframe.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/addrspace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/hazards.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/bmips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	.macro	BARRIER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	.set	mips32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	_ssnop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	_ssnop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	_ssnop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	.set	mips0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /***********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * Alternate CPU1 startup vector for BMIPS4350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * On some systems the bootloader has already started CPU1 and configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * it to resume execution at 0x8000_0200 (!BEV IV vector) when it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * triggered by the SW1 interrupt.  If that is the case we try to move
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * it to a more convenient place: BMIPS_WARM_RESTART_VEC @ 0x8000_0380.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  ***********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) LEAF(bmips_smp_movevec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	la	k0, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	li	k1, CKSEG1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	or	k0, k1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	jr	k0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	/* clear IV, pending IPIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	mtc0	zero, CP0_CAUSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	/* re-enable IRQs to wait for SW1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	li	k0, ST0_IE | ST0_BEV | STATUSF_IP1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	mtc0	k0, CP0_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	/* set up CPU1 CBR; move BASE to 0xa000_0000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	li	k0, 0xff400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	mtc0	k0, $22, 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	/* set up relocation vector address based on thread ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	mfc0	k1, $22, 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	srl	k1, 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	andi	k1, 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	or	k1, CKSEG1 | BMIPS_RELO_VECTOR_CONTROL_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	or	k0, k1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	li	k1, 0xa0080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	sw	k1, 0(k0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	/* wait here for SW1 interrupt from bmips_boot_secondary() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	la	k0, bmips_reset_nmi_vec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	li	k1, CKSEG1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	or	k0, k1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	jr	k0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) END(bmips_smp_movevec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) /***********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  * Reset/NMI vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  * For BMIPS processors that can relocate their exception vectors, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  * entire function gets copied to 0x8000_0000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  ***********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) NESTED(bmips_reset_nmi_vec, PT_SIZE, sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	.set	push
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	.set	noat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	.align	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	/* if the NMI bit is clear, assume this is a CPU1 reset instead */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	li	k1, (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	mfc0	k0, CP0_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	and	k0, k1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	beqz	k0, soft_reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #if defined(CONFIG_CPU_BMIPS5000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	mfc0	k0, CP0_PRID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	li	k1, PRID_IMP_BMIPS5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	/* mask with PRID_IMP_BMIPS5000 to cover both variants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	andi	k0, PRID_IMP_BMIPS5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	bne	k0, k1, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	/* if we're not on core 0, this must be the SMP boot signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	li	k1, (3 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	mfc0	k0, $22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	and	k0, k1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	bnez	k0, bmips_smp_entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #endif /* CONFIG_CPU_BMIPS5000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #endif /* CONFIG_SMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	/* nope, it's just a regular NMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	SAVE_ALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	move	a0, sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	/* clear EXL, ERL, BEV so that TLB refills still work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	mfc0	k0, CP0_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	li	k1, ST0_ERL | ST0_EXL | ST0_BEV | ST0_IE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	or	k0, k1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	xor	k0, k1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	mtc0	k0, CP0_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	BARRIER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	/* jump to the NMI handler function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	la	k0, nmi_handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	jr	k0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	RESTORE_ALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	.set	arch=r4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	eret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) soft_reset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #if defined(CONFIG_CPU_BMIPS5000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	mfc0	k0, CP0_PRID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	andi	k0, 0xff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	li	k1, PRID_IMP_BMIPS5200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	bne	k0, k1, bmips_smp_entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)         /* if running on TP 1, jump  to  bmips_smp_entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)         mfc0    k0, $22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)         li      k1, (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)         and     k1, k0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)         bnez    k1, bmips_smp_entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)         nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)         /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)          * running on TP0, can not be core 0 (the boot core).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)          * Check for soft reset.  Indicates a warm boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)          */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)         mfc0    k0, $12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)         li      k1, (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)         and     k0, k1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)         beqz    k0, bmips_smp_entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)         /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)          * Warm boot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)          * Cache init is only done on TP0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)          */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)         la      k0, bmips_5xxx_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)         jalr    k0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)         nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)         b       bmips_smp_entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)         nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /***********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)  * CPU1 reset vector (used for the initial boot only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)  * This is still part of bmips_reset_nmi_vec().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)  ***********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) bmips_smp_entry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	/* set up CP0 STATUS; enable FPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	li	k0, 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	mtc0	k0, CP0_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	BARRIER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	/* set local CP0 CONFIG to make kseg0 cacheable, write-back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	mfc0	k0, CP0_CONFIG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	ori	k0, 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	xori	k0, 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	mtc0	k0, CP0_CONFIG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	mfc0	k0, CP0_PRID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	andi	k0, 0xff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	li	k1, PRID_IMP_BMIPS43XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	bne	k0, k1, 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	/* initialize CPU1's local I-cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	li	k0, 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	li	k1, 0x80010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	mtc0	zero, $28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	mtc0	zero, $28, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	BARRIER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 1:	cache	Index_Store_Tag_I, 0(k0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	addiu	k0, 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	bne	k0, k1, 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	b	3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #endif /* CONFIG_CPU_BMIPS4350 || CONFIG_CPU_BMIPS4380 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #if defined(CONFIG_CPU_BMIPS5000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	/* mask with PRID_IMP_BMIPS5000 to cover both variants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	li	k1, PRID_IMP_BMIPS5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	andi	k0, PRID_IMP_BMIPS5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	bne	k0, k1, 3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	/* set exception vector base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	la	k0, ebase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	lw	k0, 0(k0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	mtc0	k0, $15, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	BARRIER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #endif /* CONFIG_CPU_BMIPS5000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	/* jump back to kseg0 in case we need to remap the kseg1 area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	la	k0, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	jr	k0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	la	k0, bmips_enable_xks01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	jalr	k0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	/* use temporary stack to set up upper memory TLB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	li	sp, BMIPS_WARM_RESTART_VEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	la	k0, plat_wired_tlb_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	jalr	k0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	/* switch to permanent stack and continue booting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	.global bmips_secondary_reentry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) bmips_secondary_reentry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	la	k0, bmips_smp_boot_sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	lw	sp, 0(k0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	la	k0, bmips_smp_boot_gp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	lw	gp, 0(k0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	la	k0, start_secondary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	jr	k0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #endif /* CONFIG_SMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.align	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.global bmips_reset_nmi_vec_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) bmips_reset_nmi_vec_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) END(bmips_reset_nmi_vec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.set	pop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /***********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)  * CPU1 warm restart vector (used for second and subsequent boots).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)  * Also used for S2 standby recovery (PM).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)  * This entire function gets copied to (BMIPS_WARM_RESTART_VEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)  ***********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) LEAF(bmips_smp_int_vec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	.align	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	mfc0	k0, CP0_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	ori	k0, 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	xori	k0, 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	mtc0	k0, CP0_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	eret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	.align	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	.global bmips_smp_int_vec_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) bmips_smp_int_vec_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) END(bmips_smp_int_vec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /***********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)  * XKS01 support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)  * Certain CPUs support extending kseg0 to 1024MB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)  ***********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) LEAF(bmips_enable_xks01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #if defined(CONFIG_XKS01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	mfc0	t0, CP0_PRID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	andi	t2, t0, 0xff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #if defined(CONFIG_CPU_BMIPS4380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	li	t1, PRID_IMP_BMIPS43XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	bne	t2, t1, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	andi	t0, 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	addiu	t1, t0, -PRID_REV_BMIPS4380_HI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	bgtz	t1, 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	addiu	t0, -PRID_REV_BMIPS4380_LO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	bltz	t0, 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	mfc0	t0, $22, 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	li	t1, 0x1ff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	li	t2, (1 << 12) | (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	or	t0, t1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	xor	t0, t1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	or	t0, t2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	mtc0	t0, $22, 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	BARRIER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	b	2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #endif /* CONFIG_CPU_BMIPS4380 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #if defined(CONFIG_CPU_BMIPS5000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	li	t1, PRID_IMP_BMIPS5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	/* mask with PRID_IMP_BMIPS5000 to cover both variants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	andi	t2, PRID_IMP_BMIPS5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	bne	t2, t1, 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	mfc0	t0, $22, 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	li	t1, 0x01ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	li	t2, (1 << 8) | (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	or	t0, t1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	xor	t0, t1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	or	t0, t2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	mtc0	t0, $22, 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	BARRIER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #endif /* CONFIG_CPU_BMIPS5000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #endif /* defined(CONFIG_XKS01) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	jr	ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) END(bmips_enable_xks01)