^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * asm-offsets.c: Calculate pt_regs and task_struct offsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1996 David S. Miller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003 Ralf Baechle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2000 MIPS Technologies, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/compat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kbuild.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/cpu-info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/smp-cps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/kvm_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) void output_ptreg_defines(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) COMMENT("MIPS pt_regs offsets.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) OFFSET(PT_R0, pt_regs, regs[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) OFFSET(PT_R1, pt_regs, regs[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) OFFSET(PT_R2, pt_regs, regs[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) OFFSET(PT_R3, pt_regs, regs[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) OFFSET(PT_R4, pt_regs, regs[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) OFFSET(PT_R5, pt_regs, regs[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) OFFSET(PT_R6, pt_regs, regs[6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) OFFSET(PT_R7, pt_regs, regs[7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) OFFSET(PT_R8, pt_regs, regs[8]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) OFFSET(PT_R9, pt_regs, regs[9]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) OFFSET(PT_R10, pt_regs, regs[10]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) OFFSET(PT_R11, pt_regs, regs[11]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) OFFSET(PT_R12, pt_regs, regs[12]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) OFFSET(PT_R13, pt_regs, regs[13]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) OFFSET(PT_R14, pt_regs, regs[14]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) OFFSET(PT_R15, pt_regs, regs[15]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) OFFSET(PT_R16, pt_regs, regs[16]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) OFFSET(PT_R17, pt_regs, regs[17]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) OFFSET(PT_R18, pt_regs, regs[18]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) OFFSET(PT_R19, pt_regs, regs[19]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) OFFSET(PT_R20, pt_regs, regs[20]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) OFFSET(PT_R21, pt_regs, regs[21]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) OFFSET(PT_R22, pt_regs, regs[22]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) OFFSET(PT_R23, pt_regs, regs[23]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) OFFSET(PT_R24, pt_regs, regs[24]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) OFFSET(PT_R25, pt_regs, regs[25]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) OFFSET(PT_R26, pt_regs, regs[26]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) OFFSET(PT_R27, pt_regs, regs[27]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) OFFSET(PT_R28, pt_regs, regs[28]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) OFFSET(PT_R29, pt_regs, regs[29]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) OFFSET(PT_R30, pt_regs, regs[30]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) OFFSET(PT_R31, pt_regs, regs[31]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) OFFSET(PT_LO, pt_regs, lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) OFFSET(PT_HI, pt_regs, hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #ifdef CONFIG_CPU_HAS_SMARTMIPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) OFFSET(PT_ACX, pt_regs, acx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) OFFSET(PT_EPC, pt_regs, cp0_epc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) OFFSET(PT_BVADDR, pt_regs, cp0_badvaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) OFFSET(PT_STATUS, pt_regs, cp0_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) OFFSET(PT_CAUSE, pt_regs, cp0_cause);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #ifdef CONFIG_CPU_CAVIUM_OCTEON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) OFFSET(PT_MPL, pt_regs, mpl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) OFFSET(PT_MTP, pt_regs, mtp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #endif /* CONFIG_CPU_CAVIUM_OCTEON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) DEFINE(PT_SIZE, sizeof(struct pt_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) void output_task_defines(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) COMMENT("MIPS task_struct offsets.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) OFFSET(TASK_STATE, task_struct, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) OFFSET(TASK_THREAD_INFO, task_struct, stack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) OFFSET(TASK_FLAGS, task_struct, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) OFFSET(TASK_MM, task_struct, mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) OFFSET(TASK_PID, task_struct, pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #if defined(CONFIG_STACKPROTECTOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) OFFSET(TASK_STACK_CANARY, task_struct, stack_canary);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) DEFINE(TASK_STRUCT_SIZE, sizeof(struct task_struct));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) void output_thread_info_defines(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) COMMENT("MIPS thread_info offsets.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) OFFSET(TI_TASK, thread_info, task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) OFFSET(TI_FLAGS, thread_info, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) OFFSET(TI_TP_VALUE, thread_info, tp_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) OFFSET(TI_CPU, thread_info, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) OFFSET(TI_PRE_COUNT, thread_info, preempt_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) OFFSET(TI_ADDR_LIMIT, thread_info, addr_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) OFFSET(TI_REGS, thread_info, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) DEFINE(_THREAD_SIZE, THREAD_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) DEFINE(_THREAD_MASK, THREAD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) DEFINE(_IRQ_STACK_SIZE, IRQ_STACK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) DEFINE(_IRQ_STACK_START, IRQ_STACK_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) void output_thread_defines(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) COMMENT("MIPS specific thread_struct offsets.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) OFFSET(THREAD_REG16, task_struct, thread.reg16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) OFFSET(THREAD_REG17, task_struct, thread.reg17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) OFFSET(THREAD_REG18, task_struct, thread.reg18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) OFFSET(THREAD_REG19, task_struct, thread.reg19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) OFFSET(THREAD_REG20, task_struct, thread.reg20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) OFFSET(THREAD_REG21, task_struct, thread.reg21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) OFFSET(THREAD_REG22, task_struct, thread.reg22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) OFFSET(THREAD_REG23, task_struct, thread.reg23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) OFFSET(THREAD_REG29, task_struct, thread.reg29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) OFFSET(THREAD_REG30, task_struct, thread.reg30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) OFFSET(THREAD_REG31, task_struct, thread.reg31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) OFFSET(THREAD_STATUS, task_struct,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) thread.cp0_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) OFFSET(THREAD_BVADDR, task_struct, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) thread.cp0_badvaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) OFFSET(THREAD_BUADDR, task_struct, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) thread.cp0_baduaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) OFFSET(THREAD_ECODE, task_struct, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) thread.error_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) OFFSET(THREAD_TRAPNO, task_struct, thread.trap_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #ifdef CONFIG_MIPS_FP_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) void output_thread_fpu_defines(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) OFFSET(THREAD_FPU, task_struct, thread.fpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) OFFSET(THREAD_FPR0, task_struct, thread.fpu.fpr[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) OFFSET(THREAD_FPR1, task_struct, thread.fpu.fpr[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) OFFSET(THREAD_FPR2, task_struct, thread.fpu.fpr[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) OFFSET(THREAD_FPR3, task_struct, thread.fpu.fpr[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) OFFSET(THREAD_FPR4, task_struct, thread.fpu.fpr[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) OFFSET(THREAD_FPR5, task_struct, thread.fpu.fpr[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) OFFSET(THREAD_FPR6, task_struct, thread.fpu.fpr[6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) OFFSET(THREAD_FPR7, task_struct, thread.fpu.fpr[7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) OFFSET(THREAD_FPR8, task_struct, thread.fpu.fpr[8]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) OFFSET(THREAD_FPR9, task_struct, thread.fpu.fpr[9]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) OFFSET(THREAD_FPR10, task_struct, thread.fpu.fpr[10]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) OFFSET(THREAD_FPR11, task_struct, thread.fpu.fpr[11]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) OFFSET(THREAD_FPR12, task_struct, thread.fpu.fpr[12]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) OFFSET(THREAD_FPR13, task_struct, thread.fpu.fpr[13]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) OFFSET(THREAD_FPR14, task_struct, thread.fpu.fpr[14]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) OFFSET(THREAD_FPR15, task_struct, thread.fpu.fpr[15]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) OFFSET(THREAD_FPR16, task_struct, thread.fpu.fpr[16]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) OFFSET(THREAD_FPR17, task_struct, thread.fpu.fpr[17]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) OFFSET(THREAD_FPR18, task_struct, thread.fpu.fpr[18]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) OFFSET(THREAD_FPR19, task_struct, thread.fpu.fpr[19]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) OFFSET(THREAD_FPR20, task_struct, thread.fpu.fpr[20]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) OFFSET(THREAD_FPR21, task_struct, thread.fpu.fpr[21]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) OFFSET(THREAD_FPR22, task_struct, thread.fpu.fpr[22]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) OFFSET(THREAD_FPR23, task_struct, thread.fpu.fpr[23]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) OFFSET(THREAD_FPR24, task_struct, thread.fpu.fpr[24]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) OFFSET(THREAD_FPR25, task_struct, thread.fpu.fpr[25]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) OFFSET(THREAD_FPR26, task_struct, thread.fpu.fpr[26]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) OFFSET(THREAD_FPR27, task_struct, thread.fpu.fpr[27]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) OFFSET(THREAD_FPR28, task_struct, thread.fpu.fpr[28]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) OFFSET(THREAD_FPR29, task_struct, thread.fpu.fpr[29]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) OFFSET(THREAD_FPR30, task_struct, thread.fpu.fpr[30]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) OFFSET(THREAD_FPR31, task_struct, thread.fpu.fpr[31]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) OFFSET(THREAD_FCR31, task_struct, thread.fpu.fcr31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) OFFSET(THREAD_MSA_CSR, task_struct, thread.fpu.msacsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) void output_mm_defines(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) COMMENT("Size of struct page");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) DEFINE(STRUCT_PAGE_SIZE, sizeof(struct page));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) COMMENT("Linux mm_struct offsets.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) OFFSET(MM_USERS, mm_struct, mm_users);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) OFFSET(MM_PGD, mm_struct, pgd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) OFFSET(MM_CONTEXT, mm_struct, context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) DEFINE(_PGD_T_SIZE, sizeof(pgd_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) DEFINE(_PMD_T_SIZE, sizeof(pmd_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) DEFINE(_PTE_T_SIZE, sizeof(pte_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) DEFINE(_PGD_T_LOG2, PGD_T_LOG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #ifndef __PAGETABLE_PMD_FOLDED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) DEFINE(_PMD_T_LOG2, PMD_T_LOG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) DEFINE(_PTE_T_LOG2, PTE_T_LOG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) DEFINE(_PGD_ORDER, PGD_ORDER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #ifndef __PAGETABLE_PMD_FOLDED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) DEFINE(_PMD_ORDER, PMD_ORDER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) DEFINE(_PTE_ORDER, PTE_ORDER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) DEFINE(_PMD_SHIFT, PMD_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) DEFINE(_PGDIR_SHIFT, PGDIR_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) DEFINE(_PTRS_PER_PGD, PTRS_PER_PGD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) DEFINE(_PTRS_PER_PMD, PTRS_PER_PMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) DEFINE(_PTRS_PER_PTE, PTRS_PER_PTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) DEFINE(_PAGE_SHIFT, PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) DEFINE(_PAGE_SIZE, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #ifdef CONFIG_32BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) void output_sc_defines(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) COMMENT("Linux sigcontext offsets.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) OFFSET(SC_REGS, sigcontext, sc_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) OFFSET(SC_FPREGS, sigcontext, sc_fpregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) OFFSET(SC_ACX, sigcontext, sc_acx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) OFFSET(SC_MDHI, sigcontext, sc_mdhi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) OFFSET(SC_MDLO, sigcontext, sc_mdlo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) OFFSET(SC_PC, sigcontext, sc_pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) OFFSET(SC_FPC_EIR, sigcontext, sc_fpc_eir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) OFFSET(SC_HI1, sigcontext, sc_hi1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) OFFSET(SC_LO1, sigcontext, sc_lo1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) OFFSET(SC_HI2, sigcontext, sc_hi2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) OFFSET(SC_LO2, sigcontext, sc_lo2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) OFFSET(SC_HI3, sigcontext, sc_hi3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) OFFSET(SC_LO3, sigcontext, sc_lo3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) void output_sc_defines(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) COMMENT("Linux sigcontext offsets.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) OFFSET(SC_REGS, sigcontext, sc_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) OFFSET(SC_FPREGS, sigcontext, sc_fpregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) OFFSET(SC_MDHI, sigcontext, sc_mdhi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) OFFSET(SC_MDLO, sigcontext, sc_mdlo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) OFFSET(SC_PC, sigcontext, sc_pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) void output_signal_defined(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) COMMENT("Linux signal numbers.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) DEFINE(_SIGHUP, SIGHUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) DEFINE(_SIGINT, SIGINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) DEFINE(_SIGQUIT, SIGQUIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) DEFINE(_SIGILL, SIGILL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) DEFINE(_SIGTRAP, SIGTRAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) DEFINE(_SIGIOT, SIGIOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) DEFINE(_SIGABRT, SIGABRT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) DEFINE(_SIGEMT, SIGEMT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) DEFINE(_SIGFPE, SIGFPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) DEFINE(_SIGKILL, SIGKILL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) DEFINE(_SIGBUS, SIGBUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) DEFINE(_SIGSEGV, SIGSEGV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) DEFINE(_SIGSYS, SIGSYS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) DEFINE(_SIGPIPE, SIGPIPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) DEFINE(_SIGALRM, SIGALRM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) DEFINE(_SIGTERM, SIGTERM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) DEFINE(_SIGUSR1, SIGUSR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) DEFINE(_SIGUSR2, SIGUSR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) DEFINE(_SIGCHLD, SIGCHLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) DEFINE(_SIGPWR, SIGPWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) DEFINE(_SIGWINCH, SIGWINCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) DEFINE(_SIGURG, SIGURG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) DEFINE(_SIGIO, SIGIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) DEFINE(_SIGSTOP, SIGSTOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) DEFINE(_SIGTSTP, SIGTSTP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) DEFINE(_SIGCONT, SIGCONT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) DEFINE(_SIGTTIN, SIGTTIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) DEFINE(_SIGTTOU, SIGTTOU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) DEFINE(_SIGVTALRM, SIGVTALRM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) DEFINE(_SIGPROF, SIGPROF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) DEFINE(_SIGXCPU, SIGXCPU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) DEFINE(_SIGXFSZ, SIGXFSZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #ifdef CONFIG_CPU_CAVIUM_OCTEON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) void output_octeon_cop2_state_defines(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) COMMENT("Octeon specific octeon_cop2_state offsets.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) OFFSET(OCTEON_CP2_CRC_IV, octeon_cop2_state, cop2_crc_iv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) OFFSET(OCTEON_CP2_CRC_LENGTH, octeon_cop2_state, cop2_crc_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) OFFSET(OCTEON_CP2_CRC_POLY, octeon_cop2_state, cop2_crc_poly);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) OFFSET(OCTEON_CP2_LLM_DAT, octeon_cop2_state, cop2_llm_dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) OFFSET(OCTEON_CP2_3DES_IV, octeon_cop2_state, cop2_3des_iv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) OFFSET(OCTEON_CP2_3DES_KEY, octeon_cop2_state, cop2_3des_key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) OFFSET(OCTEON_CP2_3DES_RESULT, octeon_cop2_state, cop2_3des_result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) OFFSET(OCTEON_CP2_AES_INP0, octeon_cop2_state, cop2_aes_inp0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) OFFSET(OCTEON_CP2_AES_IV, octeon_cop2_state, cop2_aes_iv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) OFFSET(OCTEON_CP2_AES_KEY, octeon_cop2_state, cop2_aes_key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) OFFSET(OCTEON_CP2_AES_KEYLEN, octeon_cop2_state, cop2_aes_keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) OFFSET(OCTEON_CP2_AES_RESULT, octeon_cop2_state, cop2_aes_result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) OFFSET(OCTEON_CP2_GFM_MULT, octeon_cop2_state, cop2_gfm_mult);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) OFFSET(OCTEON_CP2_GFM_POLY, octeon_cop2_state, cop2_gfm_poly);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) OFFSET(OCTEON_CP2_GFM_RESULT, octeon_cop2_state, cop2_gfm_result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) OFFSET(OCTEON_CP2_HSH_DATW, octeon_cop2_state, cop2_hsh_datw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) OFFSET(OCTEON_CP2_HSH_IVW, octeon_cop2_state, cop2_hsh_ivw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) OFFSET(OCTEON_CP2_SHA3, octeon_cop2_state, cop2_sha3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) OFFSET(THREAD_CP2, task_struct, thread.cp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) OFFSET(THREAD_CVMSEG, task_struct, thread.cvmseg.cvmseg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #ifdef CONFIG_HIBERNATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) void output_pbe_defines(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) COMMENT(" Linux struct pbe offsets. ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) OFFSET(PBE_ADDRESS, pbe, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) OFFSET(PBE_ORIG_ADDRESS, pbe, orig_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) OFFSET(PBE_NEXT, pbe, next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) DEFINE(PBE_SIZE, sizeof(struct pbe));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #ifdef CONFIG_CPU_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) void output_pm_defines(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) COMMENT(" PM offsets. ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #ifdef CONFIG_EVA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) OFFSET(SSS_SEGCTL0, mips_static_suspend_state, segctl[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) OFFSET(SSS_SEGCTL1, mips_static_suspend_state, segctl[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) OFFSET(SSS_SEGCTL2, mips_static_suspend_state, segctl[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) OFFSET(SSS_SP, mips_static_suspend_state, sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #ifdef CONFIG_MIPS_FP_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) void output_kvm_defines(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) COMMENT(" KVM/MIPS Specific offsets. ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) OFFSET(VCPU_FPR0, kvm_vcpu_arch, fpu.fpr[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) OFFSET(VCPU_FPR1, kvm_vcpu_arch, fpu.fpr[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) OFFSET(VCPU_FPR2, kvm_vcpu_arch, fpu.fpr[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) OFFSET(VCPU_FPR3, kvm_vcpu_arch, fpu.fpr[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) OFFSET(VCPU_FPR4, kvm_vcpu_arch, fpu.fpr[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) OFFSET(VCPU_FPR5, kvm_vcpu_arch, fpu.fpr[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) OFFSET(VCPU_FPR6, kvm_vcpu_arch, fpu.fpr[6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) OFFSET(VCPU_FPR7, kvm_vcpu_arch, fpu.fpr[7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) OFFSET(VCPU_FPR8, kvm_vcpu_arch, fpu.fpr[8]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) OFFSET(VCPU_FPR9, kvm_vcpu_arch, fpu.fpr[9]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) OFFSET(VCPU_FPR10, kvm_vcpu_arch, fpu.fpr[10]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) OFFSET(VCPU_FPR11, kvm_vcpu_arch, fpu.fpr[11]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) OFFSET(VCPU_FPR12, kvm_vcpu_arch, fpu.fpr[12]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) OFFSET(VCPU_FPR13, kvm_vcpu_arch, fpu.fpr[13]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) OFFSET(VCPU_FPR14, kvm_vcpu_arch, fpu.fpr[14]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) OFFSET(VCPU_FPR15, kvm_vcpu_arch, fpu.fpr[15]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) OFFSET(VCPU_FPR16, kvm_vcpu_arch, fpu.fpr[16]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) OFFSET(VCPU_FPR17, kvm_vcpu_arch, fpu.fpr[17]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) OFFSET(VCPU_FPR18, kvm_vcpu_arch, fpu.fpr[18]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) OFFSET(VCPU_FPR19, kvm_vcpu_arch, fpu.fpr[19]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) OFFSET(VCPU_FPR20, kvm_vcpu_arch, fpu.fpr[20]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) OFFSET(VCPU_FPR21, kvm_vcpu_arch, fpu.fpr[21]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) OFFSET(VCPU_FPR22, kvm_vcpu_arch, fpu.fpr[22]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) OFFSET(VCPU_FPR23, kvm_vcpu_arch, fpu.fpr[23]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) OFFSET(VCPU_FPR24, kvm_vcpu_arch, fpu.fpr[24]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) OFFSET(VCPU_FPR25, kvm_vcpu_arch, fpu.fpr[25]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) OFFSET(VCPU_FPR26, kvm_vcpu_arch, fpu.fpr[26]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) OFFSET(VCPU_FPR27, kvm_vcpu_arch, fpu.fpr[27]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) OFFSET(VCPU_FPR28, kvm_vcpu_arch, fpu.fpr[28]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) OFFSET(VCPU_FPR29, kvm_vcpu_arch, fpu.fpr[29]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) OFFSET(VCPU_FPR30, kvm_vcpu_arch, fpu.fpr[30]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) OFFSET(VCPU_FPR31, kvm_vcpu_arch, fpu.fpr[31]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) OFFSET(VCPU_FCR31, kvm_vcpu_arch, fpu.fcr31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) OFFSET(VCPU_MSA_CSR, kvm_vcpu_arch, fpu.msacsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #ifdef CONFIG_MIPS_CPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) void output_cps_defines(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) COMMENT(" MIPS CPS offsets. ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) OFFSET(COREBOOTCFG_VPEMASK, core_boot_config, vpe_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) OFFSET(COREBOOTCFG_VPECONFIG, core_boot_config, vpe_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) DEFINE(COREBOOTCFG_SIZE, sizeof(struct core_boot_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) OFFSET(VPEBOOTCFG_PC, vpe_boot_config, pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) OFFSET(VPEBOOTCFG_SP, vpe_boot_config, sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) OFFSET(VPEBOOTCFG_GP, vpe_boot_config, gp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) DEFINE(VPEBOOTCFG_SIZE, sizeof(struct vpe_boot_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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