^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1992 Linus Torvalds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1994 - 2001, 2003, 07 Ralf Baechle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/i8253.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/irq_cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/i8259.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/jazz.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/tlbmisc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static DEFINE_RAW_SPINLOCK(r4030_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static void enable_r4030_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned int mask = 1 << (d->irq - JAZZ_IRQ_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) raw_spin_lock_irqsave(&r4030_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) mask |= r4030_read_reg16(JAZZ_IO_IRQ_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) raw_spin_unlock_irqrestore(&r4030_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void disable_r4030_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned int mask = ~(1 << (d->irq - JAZZ_IRQ_START));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) raw_spin_lock_irqsave(&r4030_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) mask &= r4030_read_reg16(JAZZ_IO_IRQ_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) raw_spin_unlock_irqrestore(&r4030_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static struct irq_chip r4030_irq_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .name = "R4030",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .irq_mask = disable_r4030_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .irq_unmask = enable_r4030_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) void __init init_r4030_ints(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) for (i = JAZZ_IRQ_START; i <= JAZZ_IRQ_END; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) irq_set_chip_and_handler(i, &r4030_irq_type, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) r4030_read_reg16(JAZZ_IO_IRQ_SOURCE); /* clear pending IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) r4030_read_reg32(JAZZ_R4030_INVAL_ADDR); /* clear error bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * On systems with i8259-style interrupt controllers we assume for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * driver compatibility reasons interrupts 0 - 15 to be the i8259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * interrupts even if the hardware uses a different interrupt numbering.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) void __init arch_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * this is a hack to get back the still needed wired mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * killed by init_mm()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Map 0xe0000000 -> 0x0:800005C0, 0xe0010000 -> 0x1:30000580 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) add_wired_entry(0x02000017, 0x03c00017, 0xe0000000, PM_64K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Map 0xe2000000 -> 0x0:900005C0, 0xe3010000 -> 0x0:910005C0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) add_wired_entry(0x02400017, 0x02440017, 0xe2000000, PM_16M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Map 0xe4000000 -> 0x0:600005C0, 0xe4100000 -> 400005C0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) add_wired_entry(0x01800017, 0x01000017, 0xe4000000, PM_4M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) init_i8259_irqs(); /* Integrated i8259 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) mips_cpu_irq_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) init_r4030_ints();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) change_c0_status(ST0_IM, IE_IRQ2 | IE_IRQ1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) asmlinkage void plat_irq_dispatch(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int pending = read_c0_cause() & read_c0_status();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (pending & IE_IRQ4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) r4030_read_reg32(JAZZ_TIMER_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) do_IRQ(JAZZ_TIMER_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) } else if (pending & IE_IRQ2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) irq = *(volatile u8 *)JAZZ_EISA_IRQ_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) do_IRQ(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) } else if (pending & IE_IRQ1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) irq = *(volatile u8 *)JAZZ_IO_IRQ_SOURCE >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (likely(irq > 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) do_IRQ(irq + JAZZ_IRQ_START - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) panic("Unimplemented loc_no_irq handler");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct clock_event_device r4030_clockevent = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .name = "r4030",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .features = CLOCK_EVT_FEAT_PERIODIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .rating = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .irq = JAZZ_TIMER_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static irqreturn_t r4030_timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct clock_event_device *cd = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) cd->event_handler(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) void __init plat_time_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct clock_event_device *cd = &r4030_clockevent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) BUG_ON(HZ != 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) cd->cpumask = cpumask_of(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) clockevents_register_device(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (request_irq(JAZZ_TIMER_IRQ, r4030_timer_interrupt, IRQF_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) "R4030 timer", cd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) pr_err("Failed to register R4030 timer interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * Set clock to 100Hz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * The R4030 timer receives an input clock of 1kHz which is divieded by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * a programmable 4-bit divider. This makes it fairly inflexible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) r4030_write_reg32(JAZZ_TIMER_INTERVAL, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) setup_pit_timer();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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