Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (C) 1996 David S. Miller (dm@sgi.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Compatibility with board caches, Ulf Carlsson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/sgialib.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/bcache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #if defined(CONFIG_64BIT) && defined(CONFIG_FW_ARC32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * For 64bit kernels working with a 32bit ARC PROM pointer arguments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * for ARC calls need to reside in CKEG0/1. But as soon as the kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  * switches to it's first kernel thread stack is set to an address in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  * XKPHYS, so anything on stack can't be used anymore. This is solved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  * by using a * static declartion variables are put into BSS, which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  * linked to a CKSEG0 address. Since this is only used on UP platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  * there is not spinlock needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define O32_STATIC	static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define O32_STATIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)  * IP22 boardcache is not compatible with board caches.	 Thus we disable it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)  * during romvec action.  Since r4xx0.c is always compiled and linked with your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)  * kernel, this shouldn't cause any harm regardless what MIPS processor you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)  * have.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)  * The ARC write and read functions seem to interfere with the serial lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)  * in some way. You should be careful with them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) void prom_putchar(char c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	O32_STATIC ULONG cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	O32_STATIC CHAR it;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	it = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	bc_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	ArcWrite(1, &it, 1, &cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	bc_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) char prom_getchar(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	O32_STATIC ULONG cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	O32_STATIC CHAR c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	bc_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	ArcRead(0, &c, 1, &cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	bc_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	return c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }