^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 1991, 1992, 1995 Linus Torvalds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2000, 2003 Maciej W. Rozycki
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file contains the time handling details for PC-style clocks as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * found in some MIPS systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mc146818rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/param.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/cpu-features.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/ds1287.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/dec/interrupts.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/dec/ioasic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/dec/machtype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) void read_persistent_clock64(struct timespec64 *ts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) unsigned int year, mon, day, hour, min, sec, real_year;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) spin_lock_irqsave(&rtc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) sec = CMOS_READ(RTC_SECONDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) min = CMOS_READ(RTC_MINUTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) hour = CMOS_READ(RTC_HOURS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) day = CMOS_READ(RTC_DAY_OF_MONTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) mon = CMOS_READ(RTC_MONTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) year = CMOS_READ(RTC_YEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * The PROM will reset the year to either '72 or '73.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Therefore we store the real year separately, in one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * of unused BBU RAM locations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) real_year = CMOS_READ(RTC_DEC_YEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) } while (sec != CMOS_READ(RTC_SECONDS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) spin_unlock_irqrestore(&rtc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) sec = bcd2bin(sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) min = bcd2bin(min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) hour = bcd2bin(hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) day = bcd2bin(day);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) mon = bcd2bin(mon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) year = bcd2bin(year);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) year += real_year - 72 + 2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ts->tv_sec = mktime64(year, mon, day, hour, min, sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ts->tv_nsec = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * In order to set the CMOS clock precisely, update_persistent_clock64 has to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * be called 500 ms after the second nowtime has started, because when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * nowtime is written into the registers of the CMOS clock, it will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * jump to the next second precisely 500 ms later. Check the Dallas
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * DS1287 data sheet for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int update_persistent_clock64(struct timespec64 now)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) time64_t nowtime = now.tv_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int real_seconds, real_minutes, cmos_minutes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned char save_control, save_freq_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* irq are locally disabled here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) spin_lock(&rtc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* tell the clock it's being set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) save_control = CMOS_READ(RTC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) CMOS_WRITE((save_control | RTC_SET), RTC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* stop and reset prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) CMOS_WRITE((save_freq_select | RTC_DIV_RESET2), RTC_FREQ_SELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) cmos_minutes = CMOS_READ(RTC_MINUTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) cmos_minutes = bcd2bin(cmos_minutes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * since we're only adjusting minutes and seconds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * don't interfere with hour overflow. This avoids
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * messing with unknown time zones but requires your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * RTC not to be off by more than 15 minutes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) real_minutes = div_s64_rem(nowtime, 60, &real_seconds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (((abs(real_minutes - cmos_minutes) + 15) / 30) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) real_minutes += 30; /* correct for half hour time zone */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) real_minutes %= 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (abs(real_minutes - cmos_minutes) < 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) real_seconds = bin2bcd(real_seconds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) real_minutes = bin2bcd(real_minutes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) CMOS_WRITE(real_seconds, RTC_SECONDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) CMOS_WRITE(real_minutes, RTC_MINUTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) printk_once(KERN_NOTICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) "set_rtc_mmss: can't update from %d to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) cmos_minutes, real_minutes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) retval = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* The following flags have to be released exactly in this order,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * otherwise the DS1287 will not reset the oscillator and will not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * update precisely 500 ms later. You won't find this mentioned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * in the Dallas Semiconductor data sheets, but who believes data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * sheets anyway ... -- Markus Kuhn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) CMOS_WRITE(save_control, RTC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) spin_unlock(&rtc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) void __init plat_time_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int ioasic_clock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 start, end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int i = HZ / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Set up the rate of periodic DS1287 interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ds1287_set_base_clock(HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* On some I/O ASIC systems we have the I/O ASIC's counter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (IOASIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ioasic_clock = dec_ioasic_clocksource_init() == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (cpu_has_counter) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ds1287_timer_state();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) while (!ds1287_timer_state())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) start = read_c0_count();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) while (i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) while (!ds1287_timer_state())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) end = read_c0_count();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) mips_hpt_frequency = (end - start) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) printk(KERN_INFO "MIPS counter frequency %dHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) mips_hpt_frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * All R4k DECstations suffer from the CP0 Count erratum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * so we can't use the timer as a clock source, and a clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * event both at a time. An accurate wall clock is more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * important than a high-precision interval timer so only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * use the timer as a clock source, and not a clock event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * if there's no I/O ASIC counter available to serve as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * clock source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (!ioasic_clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) init_r4k_clocksource();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) mips_hpt_frequency = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ds1287_clockevent_init(dec_interrupt[DEC_IRQ_RTC]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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