Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  *	TURBOchannel architecture calls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *	Copyright (c) Harald Koerfgen, 1998
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *	Copyright (c) 2001, 2003, 2005, 2006  Maciej W. Rozycki
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *	Copyright (c) 2005  James Simmons
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *	This file is subject to the terms and conditions of the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *	General Public License.  See the file "COPYING" in the main
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *	directory of this archive for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/tc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/addrspace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/bootinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/paccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/dec/interrupts.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/dec/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/dec/system.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  * Protected read byte from TURBOchannel slot space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int tc_preadb(u8 *valp, void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	return get_dbe(*valp, (u8 *)addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)  * Get TURBOchannel bus information as specified by the spec, plus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)  * the slot space base address and the number of slots.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int __init tc_bus_get_info(struct tc_bus *tbus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	if (!dec_tc_bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	memcpy(&tbus->info, rex_gettcinfo(), sizeof(tbus->info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	tbus->slot_base = CPHYSADDR((long)rex_slot_address(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	switch (mips_machtype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	case MACH_DS5000_200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		tbus->num_tcslots = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	case MACH_DS5000_2X0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	case MACH_DS5900:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		tbus->ext_slot_base = 0x20000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		tbus->ext_slot_size = 0x20000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	case MACH_DS5000_1XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		tbus->num_tcslots = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	case MACH_DS5000_XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		tbus->num_tcslots = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)  * Get the IRQ for the specified slot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) void __init tc_device_get_irq(struct tc_dev *tdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	switch (tdev->slot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 		tdev->interrupt = dec_interrupt[DEC_IRQ_TC0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 		tdev->interrupt = dec_interrupt[DEC_IRQ_TC1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 		tdev->interrupt = dec_interrupt[DEC_IRQ_TC2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 	 * Yuck! DS5000/200 onboard devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 	case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 		tdev->interrupt = dec_interrupt[DEC_IRQ_TC5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 	case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 		tdev->interrupt = dec_interrupt[DEC_IRQ_TC6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 		tdev->interrupt = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }