^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * System-specific setup, especially interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 1998 Harald Koerfgen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2000, 2001, 2002, 2003, 2005, 2020 Maciej W. Rozycki
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/irqnr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/param.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/percpu-defs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/addrspace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/bootinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/cpu-features.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/cpu-type.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/irq_cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/sections.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/traps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <asm/wbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <asm/dec/interrupts.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <asm/dec/ioasic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <asm/dec/ioasic_addrs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <asm/dec/ioasic_ints.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <asm/dec/kn01.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <asm/dec/kn02.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <asm/dec/kn02ba.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <asm/dec/kn02ca.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <asm/dec/kn03.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <asm/dec/kn230.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <asm/dec/system.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) extern void dec_machine_restart(char *command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) extern void dec_machine_halt(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) extern void dec_machine_power_off(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) extern irqreturn_t dec_intr_halt(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned long dec_kn_slot_base, dec_kn_slot_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) EXPORT_SYMBOL(dec_kn_slot_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) EXPORT_SYMBOL(dec_kn_slot_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int dec_tc_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) DEFINE_SPINLOCK(ioasic_ssr_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) EXPORT_SYMBOL(ioasic_ssr_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) volatile u32 *ioasic_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) EXPORT_SYMBOL(ioasic_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * IRQ routing and priority tables. Priorites are set as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * KN01 KN230 KN02 KN02-BA KN02-CA KN03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * MEMORY CPU CPU CPU ASIC CPU CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * RTC CPU CPU CPU ASIC CPU CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * DMA - - - ASIC ASIC ASIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * SERIAL0 CPU CPU CSR ASIC ASIC ASIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * SERIAL1 - - - ASIC - ASIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * SCSI CPU CPU CSR ASIC ASIC ASIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * ETHERNET CPU * CSR ASIC ASIC ASIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * other - - - ASIC - -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * TC2 - - CSR CPU ASIC ASIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * TC1 - - CSR CPU ASIC ASIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * TC0 - - CSR CPU ASIC ASIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * other - CPU - CPU ASIC ASIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * other - - - - CPU CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * * -- shared with SCSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int dec_interrupt[DEC_NR_INTS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) [0 ... DEC_NR_INTS - 1] = -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) EXPORT_SYMBOL(dec_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { { .i = ~0 }, { .p = dec_intr_unimplemented } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { { .i = ~0 }, { .p = asic_intr_unimplemented } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int *fpu_kstat_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static irq_handler_t busirq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static unsigned int busirq_flags = IRQF_NO_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * Bus error (DBE/IBE exceptions and bus interrupts) handling setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static void __init dec_be_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) switch (mips_machtype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) board_be_handler = dec_kn01_be_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) busirq_handler = dec_kn01_be_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) busirq_flags |= IRQF_SHARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dec_kn01_be_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) case MACH_DS5000_1XX: /* DS5000/1xx 3min */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) case MACH_DS5000_XX: /* DS5000/xx Maxine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) board_be_handler = dec_kn02xa_be_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) busirq_handler = dec_kn02xa_be_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) dec_kn02xa_be_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) case MACH_DS5000_200: /* DS5000/200 3max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) case MACH_DS5000_2X0: /* DS5000/240 3max+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) case MACH_DS5900: /* DS5900 bigmax */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) board_be_handler = dec_ecc_be_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) busirq_handler = dec_ecc_be_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) dec_ecc_be_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) void __init plat_mem_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) board_be_init = dec_be_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) wbflush_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) _machine_restart = dec_machine_restart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) _machine_halt = dec_machine_halt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) pm_power_off = dec_machine_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ioport_resource.start = ~0UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ioport_resource.end = 0UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Stay away from the firmware working memory area for now. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) memblock_reserve(PHYS_OFFSET, __pa_symbol(&_text) - PHYS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * Machine-specific initialisation for KN01, aka DS2100 (aka Pmin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * or DS3100 (aka Pmax).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int kn01_interrupt[DEC_NR_INTS] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) [DEC_IRQ_CASCADE] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) [DEC_IRQ_AB_RECV] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) [DEC_IRQ_AB_XMIT] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) [DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) [DEC_IRQ_ASC] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) [DEC_IRQ_FLOPPY] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) [DEC_IRQ_HALT] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) [DEC_IRQ_ISDN] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) [DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) [DEC_IRQ_PSU] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) [DEC_IRQ_SCC0] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) [DEC_IRQ_SCC1] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) [DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) [DEC_IRQ_TC0] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) [DEC_IRQ_TC1] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) [DEC_IRQ_TC2] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) [DEC_IRQ_TIMER] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) [DEC_IRQ_VIDEO] = DEC_CPU_IRQ_NR(KN01_CPU_INR_VIDEO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) [DEC_IRQ_ASC_MERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) [DEC_IRQ_ASC_ERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) [DEC_IRQ_ASC_DMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) [DEC_IRQ_FLOPPY_ERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) [DEC_IRQ_ISDN_ERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) [DEC_IRQ_ISDN_RXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) [DEC_IRQ_ISDN_TXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) [DEC_IRQ_LANCE_MERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) [DEC_IRQ_SCC0A_RXERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) [DEC_IRQ_SCC0A_RXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) [DEC_IRQ_SCC0A_TXERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) [DEC_IRQ_SCC0A_TXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) [DEC_IRQ_AB_RXERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) [DEC_IRQ_AB_RXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) [DEC_IRQ_AB_TXERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) [DEC_IRQ_AB_TXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) [DEC_IRQ_SCC1A_RXERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) [DEC_IRQ_SCC1A_RXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) [DEC_IRQ_SCC1A_TXERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) [DEC_IRQ_SCC1A_TXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int_ptr kn01_cpu_mask_nr_tbl[][2] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_BUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_RTC) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_DZ11) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_SII) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_LANCE) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { { .i = DEC_CPU_IRQ_ALL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { .p = cpu_all_int } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static void __init dec_init_kn01(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* IRQ routing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) memcpy(&dec_interrupt, &kn01_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) sizeof(kn01_interrupt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* CPU IRQ priorities. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) sizeof(kn01_cpu_mask_nr_tbl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) mips_cpu_irq_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) } /* dec_init_kn01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * Machine-specific initialisation for KN230, aka DS5100, aka MIPSmate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int kn230_interrupt[DEC_NR_INTS] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) [DEC_IRQ_CASCADE] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) [DEC_IRQ_AB_RECV] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) [DEC_IRQ_AB_XMIT] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) [DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) [DEC_IRQ_ASC] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) [DEC_IRQ_FLOPPY] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN230_CPU_INR_HALT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) [DEC_IRQ_ISDN] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) [DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN230_CPU_INR_LANCE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) [DEC_IRQ_PSU] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) [DEC_IRQ_SCC0] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) [DEC_IRQ_SCC1] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) [DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) [DEC_IRQ_TC0] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) [DEC_IRQ_TC1] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) [DEC_IRQ_TC2] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) [DEC_IRQ_TIMER] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) [DEC_IRQ_VIDEO] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) [DEC_IRQ_ASC_MERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) [DEC_IRQ_ASC_ERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) [DEC_IRQ_ASC_DMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) [DEC_IRQ_FLOPPY_ERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) [DEC_IRQ_ISDN_ERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) [DEC_IRQ_ISDN_RXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) [DEC_IRQ_ISDN_TXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) [DEC_IRQ_LANCE_MERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) [DEC_IRQ_SCC0A_RXERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) [DEC_IRQ_SCC0A_RXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) [DEC_IRQ_SCC0A_TXERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) [DEC_IRQ_SCC0A_TXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) [DEC_IRQ_AB_RXERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) [DEC_IRQ_AB_RXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) [DEC_IRQ_AB_TXERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) [DEC_IRQ_AB_TXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) [DEC_IRQ_SCC1A_RXERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) [DEC_IRQ_SCC1A_RXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) [DEC_IRQ_SCC1A_TXERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) [DEC_IRQ_SCC1A_TXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int_ptr kn230_cpu_mask_nr_tbl[][2] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_BUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_RTC) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_DZ11) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_SII) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) { { .i = DEC_CPU_IRQ_ALL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) { .p = cpu_all_int } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static void __init dec_init_kn230(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* IRQ routing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) memcpy(&dec_interrupt, &kn230_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) sizeof(kn230_interrupt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* CPU IRQ priorities. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) sizeof(kn230_cpu_mask_nr_tbl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) mips_cpu_irq_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) } /* dec_init_kn230 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * Machine-specific initialisation for KN02, aka DS5000/200, aka 3max.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int kn02_interrupt[DEC_NR_INTS] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02_CPU_INR_CASCADE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) [DEC_IRQ_AB_RECV] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) [DEC_IRQ_AB_XMIT] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) [DEC_IRQ_DZ11] = KN02_IRQ_NR(KN02_CSR_INR_DZ11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) [DEC_IRQ_ASC] = KN02_IRQ_NR(KN02_CSR_INR_ASC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) [DEC_IRQ_FLOPPY] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) [DEC_IRQ_HALT] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) [DEC_IRQ_ISDN] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) [DEC_IRQ_LANCE] = KN02_IRQ_NR(KN02_CSR_INR_LANCE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) [DEC_IRQ_PSU] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) [DEC_IRQ_SCC0] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) [DEC_IRQ_SCC1] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) [DEC_IRQ_SII] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) [DEC_IRQ_TC0] = KN02_IRQ_NR(KN02_CSR_INR_TC0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) [DEC_IRQ_TC1] = KN02_IRQ_NR(KN02_CSR_INR_TC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) [DEC_IRQ_TC2] = KN02_IRQ_NR(KN02_CSR_INR_TC2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) [DEC_IRQ_TIMER] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) [DEC_IRQ_VIDEO] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) [DEC_IRQ_ASC_MERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) [DEC_IRQ_ASC_ERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) [DEC_IRQ_ASC_DMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) [DEC_IRQ_FLOPPY_ERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) [DEC_IRQ_ISDN_ERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) [DEC_IRQ_ISDN_RXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) [DEC_IRQ_ISDN_TXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) [DEC_IRQ_LANCE_MERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) [DEC_IRQ_SCC0A_RXERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) [DEC_IRQ_SCC0A_RXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) [DEC_IRQ_SCC0A_TXERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) [DEC_IRQ_SCC0A_TXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) [DEC_IRQ_AB_RXERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) [DEC_IRQ_AB_RXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) [DEC_IRQ_AB_TXERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) [DEC_IRQ_AB_TXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) [DEC_IRQ_SCC1A_RXERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) [DEC_IRQ_SCC1A_RXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) [DEC_IRQ_SCC1A_TXERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) [DEC_IRQ_SCC1A_TXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int_ptr kn02_cpu_mask_nr_tbl[][2] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_BUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_RTC) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_CASCADE) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) { .p = kn02_io_int } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) { { .i = DEC_CPU_IRQ_ALL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) { .p = cpu_all_int } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static int_ptr kn02_asic_mask_nr_tbl[][2] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) { { .i = KN02_IRQ_MASK(KN02_CSR_INR_DZ11) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) { .i = KN02_IRQ_NR(KN02_CSR_INR_DZ11) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) { { .i = KN02_IRQ_MASK(KN02_CSR_INR_ASC) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) { .i = KN02_IRQ_NR(KN02_CSR_INR_ASC) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) { { .i = KN02_IRQ_MASK(KN02_CSR_INR_LANCE) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) { .i = KN02_IRQ_NR(KN02_CSR_INR_LANCE) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) { .i = KN02_IRQ_NR(KN02_CSR_INR_TC2) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) { .i = KN02_IRQ_NR(KN02_CSR_INR_TC1) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) { .i = KN02_IRQ_NR(KN02_CSR_INR_TC0) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) { { .i = KN02_IRQ_ALL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) { .p = kn02_all_int } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static void __init dec_init_kn02(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* IRQ routing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) memcpy(&dec_interrupt, &kn02_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) sizeof(kn02_interrupt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* CPU IRQ priorities. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) memcpy(&cpu_mask_nr_tbl, &kn02_cpu_mask_nr_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) sizeof(kn02_cpu_mask_nr_tbl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* KN02 CSR IRQ priorities. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) sizeof(kn02_asic_mask_nr_tbl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) mips_cpu_irq_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) init_kn02_irqs(KN02_IRQ_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) } /* dec_init_kn02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * Machine-specific initialisation for KN02-BA, aka DS5000/1xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * (xx = 20, 25, 33), aka 3min. Also applies to KN04(-BA), aka
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * DS5000/150, aka 4min.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static int kn02ba_interrupt[DEC_NR_INTS] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_CASCADE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) [DEC_IRQ_AB_RECV] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) [DEC_IRQ_AB_XMIT] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) [DEC_IRQ_DZ11] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) [DEC_IRQ_ASC] = IO_IRQ_NR(KN02BA_IO_INR_ASC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) [DEC_IRQ_FLOPPY] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_HALT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) [DEC_IRQ_ISDN] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) [DEC_IRQ_LANCE] = IO_IRQ_NR(KN02BA_IO_INR_LANCE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) [DEC_IRQ_BUS] = IO_IRQ_NR(KN02BA_IO_INR_BUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) [DEC_IRQ_PSU] = IO_IRQ_NR(KN02BA_IO_INR_PSU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) [DEC_IRQ_RTC] = IO_IRQ_NR(KN02BA_IO_INR_RTC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) [DEC_IRQ_SCC0] = IO_IRQ_NR(KN02BA_IO_INR_SCC0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) [DEC_IRQ_SCC1] = IO_IRQ_NR(KN02BA_IO_INR_SCC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) [DEC_IRQ_SII] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) [DEC_IRQ_TC0] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) [DEC_IRQ_TC1] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) [DEC_IRQ_TC2] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) [DEC_IRQ_TIMER] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) [DEC_IRQ_VIDEO] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) [DEC_IRQ_FLOPPY_ERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) [DEC_IRQ_ISDN_ERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) [DEC_IRQ_ISDN_RXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) [DEC_IRQ_ISDN_TXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) [DEC_IRQ_AB_RXERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) [DEC_IRQ_AB_RXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) [DEC_IRQ_AB_TXERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) [DEC_IRQ_AB_TXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) [DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) [DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) [DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) [DEC_IRQ_SCC1A_TXDMA] = IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static int_ptr kn02ba_cpu_mask_nr_tbl[][2] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_CASCADE) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) { .p = kn02xa_io_int } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) { { .i = DEC_CPU_IRQ_ALL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) { .p = cpu_all_int } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static int_ptr kn02ba_asic_mask_nr_tbl[][2] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) { { .i = IO_IRQ_MASK(KN02BA_IO_INR_BUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) { .i = IO_IRQ_NR(KN02BA_IO_INR_BUS) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) { { .i = IO_IRQ_MASK(KN02BA_IO_INR_RTC) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) { .i = IO_IRQ_NR(KN02BA_IO_INR_RTC) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) { { .i = IO_IRQ_DMA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) { .p = asic_dma_int } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC0) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC1) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) { { .i = IO_IRQ_MASK(KN02BA_IO_INR_ASC) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) { .i = IO_IRQ_NR(KN02BA_IO_INR_ASC) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) { { .i = IO_IRQ_MASK(KN02BA_IO_INR_LANCE) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) { .i = IO_IRQ_NR(KN02BA_IO_INR_LANCE) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) { { .i = IO_IRQ_ALL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) { .p = asic_all_int } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static void __init dec_init_kn02ba(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* IRQ routing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) memcpy(&dec_interrupt, &kn02ba_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) sizeof(kn02ba_interrupt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* CPU IRQ priorities. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) memcpy(&cpu_mask_nr_tbl, &kn02ba_cpu_mask_nr_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) sizeof(kn02ba_cpu_mask_nr_tbl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* I/O ASIC IRQ priorities. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) sizeof(kn02ba_asic_mask_nr_tbl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) mips_cpu_irq_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) init_ioasic_irqs(IO_IRQ_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) } /* dec_init_kn02ba */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * Machine-specific initialisation for KN02-CA, aka DS5000/xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * (xx = 20, 25, 33), aka MAXine. Also applies to KN04(-CA), aka
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * DS5000/50, aka 4MAXine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static int kn02ca_interrupt[DEC_NR_INTS] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_CASCADE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) [DEC_IRQ_AB_RECV] = IO_IRQ_NR(KN02CA_IO_INR_AB_RECV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) [DEC_IRQ_AB_XMIT] = IO_IRQ_NR(KN02CA_IO_INR_AB_XMIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) [DEC_IRQ_DZ11] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) [DEC_IRQ_ASC] = IO_IRQ_NR(KN02CA_IO_INR_ASC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) [DEC_IRQ_FLOPPY] = IO_IRQ_NR(KN02CA_IO_INR_FLOPPY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_HALT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) [DEC_IRQ_ISDN] = IO_IRQ_NR(KN02CA_IO_INR_ISDN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) [DEC_IRQ_LANCE] = IO_IRQ_NR(KN02CA_IO_INR_LANCE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) [DEC_IRQ_PSU] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) [DEC_IRQ_SCC0] = IO_IRQ_NR(KN02CA_IO_INR_SCC0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) [DEC_IRQ_SCC1] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) [DEC_IRQ_SII] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) [DEC_IRQ_TC0] = IO_IRQ_NR(KN02CA_IO_INR_TC0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) [DEC_IRQ_TC1] = IO_IRQ_NR(KN02CA_IO_INR_TC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) [DEC_IRQ_TC2] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) [DEC_IRQ_TIMER] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_TIMER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) [DEC_IRQ_VIDEO] = IO_IRQ_NR(KN02CA_IO_INR_VIDEO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) [DEC_IRQ_FLOPPY_ERR] = IO_IRQ_NR(IO_INR_FLOPPY_ERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) [DEC_IRQ_ISDN_ERR] = IO_IRQ_NR(IO_INR_ISDN_ERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) [DEC_IRQ_ISDN_RXDMA] = IO_IRQ_NR(IO_INR_ISDN_RXDMA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) [DEC_IRQ_ISDN_TXDMA] = IO_IRQ_NR(IO_INR_ISDN_TXDMA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) [DEC_IRQ_AB_RXERR] = IO_IRQ_NR(IO_INR_AB_RXERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) [DEC_IRQ_AB_RXDMA] = IO_IRQ_NR(IO_INR_AB_RXDMA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) [DEC_IRQ_AB_TXERR] = IO_IRQ_NR(IO_INR_AB_TXERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) [DEC_IRQ_AB_TXDMA] = IO_IRQ_NR(IO_INR_AB_TXDMA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) [DEC_IRQ_SCC1A_RXERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) [DEC_IRQ_SCC1A_RXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) [DEC_IRQ_SCC1A_TXERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) [DEC_IRQ_SCC1A_TXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static int_ptr kn02ca_cpu_mask_nr_tbl[][2] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_BUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_RTC) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_CASCADE) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) { .p = kn02xa_io_int } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) { { .i = DEC_CPU_IRQ_ALL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) { .p = cpu_all_int } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static int_ptr kn02ca_asic_mask_nr_tbl[][2] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) { { .i = IO_IRQ_DMA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) { .p = asic_dma_int } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) { { .i = IO_IRQ_MASK(KN02CA_IO_INR_SCC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) { .i = IO_IRQ_NR(KN02CA_IO_INR_SCC0) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) { { .i = IO_IRQ_MASK(KN02CA_IO_INR_ASC) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) { .i = IO_IRQ_NR(KN02CA_IO_INR_ASC) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) { { .i = IO_IRQ_MASK(KN02CA_IO_INR_LANCE) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) { .i = IO_IRQ_NR(KN02CA_IO_INR_LANCE) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) { .i = IO_IRQ_NR(KN02CA_IO_INR_TC1) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) { .i = IO_IRQ_NR(KN02CA_IO_INR_TC0) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) { { .i = IO_IRQ_ALL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) { .p = asic_all_int } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static void __init dec_init_kn02ca(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* IRQ routing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) memcpy(&dec_interrupt, &kn02ca_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) sizeof(kn02ca_interrupt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* CPU IRQ priorities. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) memcpy(&cpu_mask_nr_tbl, &kn02ca_cpu_mask_nr_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) sizeof(kn02ca_cpu_mask_nr_tbl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* I/O ASIC IRQ priorities. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) sizeof(kn02ca_asic_mask_nr_tbl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) mips_cpu_irq_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) init_ioasic_irqs(IO_IRQ_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) } /* dec_init_kn02ca */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * Machine-specific initialisation for KN03, aka DS5000/240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * aka 3max+ and DS5900, aka BIGmax. Also applies to KN05, aka
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * DS5000/260, aka 4max+ and DS5900/260.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static int kn03_interrupt[DEC_NR_INTS] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN03_CPU_INR_CASCADE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) [DEC_IRQ_AB_RECV] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) [DEC_IRQ_AB_XMIT] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) [DEC_IRQ_DZ11] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) [DEC_IRQ_ASC] = IO_IRQ_NR(KN03_IO_INR_ASC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) [DEC_IRQ_FLOPPY] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN03_CPU_INR_HALT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) [DEC_IRQ_ISDN] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) [DEC_IRQ_LANCE] = IO_IRQ_NR(KN03_IO_INR_LANCE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) [DEC_IRQ_PSU] = IO_IRQ_NR(KN03_IO_INR_PSU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) [DEC_IRQ_SCC0] = IO_IRQ_NR(KN03_IO_INR_SCC0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) [DEC_IRQ_SCC1] = IO_IRQ_NR(KN03_IO_INR_SCC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) [DEC_IRQ_SII] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) [DEC_IRQ_TC0] = IO_IRQ_NR(KN03_IO_INR_TC0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) [DEC_IRQ_TC1] = IO_IRQ_NR(KN03_IO_INR_TC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) [DEC_IRQ_TC2] = IO_IRQ_NR(KN03_IO_INR_TC2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) [DEC_IRQ_TIMER] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) [DEC_IRQ_VIDEO] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) [DEC_IRQ_FLOPPY_ERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) [DEC_IRQ_ISDN_ERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) [DEC_IRQ_ISDN_RXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) [DEC_IRQ_ISDN_TXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) [DEC_IRQ_AB_RXERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) [DEC_IRQ_AB_RXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) [DEC_IRQ_AB_TXERR] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) [DEC_IRQ_AB_TXDMA] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) [DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) [DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) [DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) [DEC_IRQ_SCC1A_TXDMA] = IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static int_ptr kn03_cpu_mask_nr_tbl[][2] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_BUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_RTC) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_CASCADE) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) { .p = kn03_io_int } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) { { .i = DEC_CPU_IRQ_ALL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) { .p = cpu_all_int } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static int_ptr kn03_asic_mask_nr_tbl[][2] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) { { .i = IO_IRQ_DMA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) { .p = asic_dma_int } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) { .i = IO_IRQ_NR(KN03_IO_INR_SCC0) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) { .i = IO_IRQ_NR(KN03_IO_INR_SCC1) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) { { .i = IO_IRQ_MASK(KN03_IO_INR_ASC) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) { .i = IO_IRQ_NR(KN03_IO_INR_ASC) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) { { .i = IO_IRQ_MASK(KN03_IO_INR_LANCE) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) { .i = IO_IRQ_NR(KN03_IO_INR_LANCE) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) { { .i = IO_IRQ_MASK(KN03_IO_INR_TC2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) { .i = IO_IRQ_NR(KN03_IO_INR_TC2) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) { { .i = IO_IRQ_MASK(KN03_IO_INR_TC1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) { .i = IO_IRQ_NR(KN03_IO_INR_TC1) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) { { .i = IO_IRQ_MASK(KN03_IO_INR_TC0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) { .i = IO_IRQ_NR(KN03_IO_INR_TC0) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) { { .i = IO_IRQ_ALL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) { .p = asic_all_int } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static void __init dec_init_kn03(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /* IRQ routing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) memcpy(&dec_interrupt, &kn03_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) sizeof(kn03_interrupt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* CPU IRQ priorities. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) memcpy(&cpu_mask_nr_tbl, &kn03_cpu_mask_nr_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) sizeof(kn03_cpu_mask_nr_tbl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* I/O ASIC IRQ priorities. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) sizeof(kn03_asic_mask_nr_tbl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) mips_cpu_irq_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) init_ioasic_irqs(IO_IRQ_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) } /* dec_init_kn03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) void __init arch_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) switch (mips_machtype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) dec_init_kn01();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) case MACH_DS5100: /* DS5100 MIPSmate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) dec_init_kn230();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) case MACH_DS5000_200: /* DS5000/200 3max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) dec_init_kn02();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) case MACH_DS5000_1XX: /* DS5000/1xx 3min */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) dec_init_kn02ba();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) case MACH_DS5000_2X0: /* DS5000/240 3max+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) case MACH_DS5900: /* DS5900 bigmax */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) dec_init_kn03();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) case MACH_DS5000_XX: /* Personal DS5000/xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) dec_init_kn02ca();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) case MACH_DS5800: /* DS5800 Isis */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) panic("Don't know how to set this up!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) case MACH_DS5400: /* DS5400 MIPSfair */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) panic("Don't know how to set this up!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) case MACH_DS5500: /* DS5500 MIPSfair-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) panic("Don't know how to set this up!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* Free the FPU interrupt if the exception is present. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (!cpu_has_nofpuex) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) cpu_fpu_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) dec_interrupt[DEC_IRQ_FPU] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* Free the halt interrupt unused on R4k systems. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (current_cpu_type() == CPU_R4000SC ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) current_cpu_type() == CPU_R4400SC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) dec_interrupt[DEC_IRQ_HALT] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* Register board interrupts: FPU and cascade. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (IS_ENABLED(CONFIG_MIPS_FP_SUPPORT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) dec_interrupt[DEC_IRQ_FPU] >= 0 && cpu_has_fpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct irq_desc *desc_fpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) int irq_fpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) irq_fpu = dec_interrupt[DEC_IRQ_FPU];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (request_irq(irq_fpu, no_action, IRQF_NO_THREAD, "fpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) pr_err("Failed to register fpu interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) desc_fpu = irq_to_desc(irq_fpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) fpu_kstat_irq = this_cpu_ptr(desc_fpu->kstat_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (dec_interrupt[DEC_IRQ_CASCADE] >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (request_irq(dec_interrupt[DEC_IRQ_CASCADE], no_action,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) IRQF_NO_THREAD, "cascade", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) pr_err("Failed to register cascade interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /* Register the bus error interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (dec_interrupt[DEC_IRQ_BUS] >= 0 && busirq_handler) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (request_irq(dec_interrupt[DEC_IRQ_BUS], busirq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) busirq_flags, "bus error", busirq_handler))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) pr_err("Failed to register bus error interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* Register the HALT interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (dec_interrupt[DEC_IRQ_HALT] >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (request_irq(dec_interrupt[DEC_IRQ_HALT], dec_intr_halt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) IRQF_NO_THREAD, "halt", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) pr_err("Failed to register halt interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) asmlinkage unsigned int dec_irq_dispatch(unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) do_IRQ(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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