Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *	DECstation 5000/200 (KN02) Control and Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *	interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *	Copyright (c) 2002, 2003, 2005  Maciej W. Rozycki
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/dec/kn02.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * Bits 7:0 of the Control Register are write-only -- the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  * corresponding bits of the Status Register have a different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  * meaning.  Hence we use a cache.  It speeds up things a bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  * as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  * There is no default value -- it has to be initialized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u32 cached_kn02_csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static int kn02_irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static void unmask_kn02_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 						       KN02_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	cached_kn02_csr |= (1 << (d->irq - kn02_irq_base + 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	*csr = cached_kn02_csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static void mask_kn02_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 						       KN02_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	cached_kn02_csr &= ~(1 << (d->irq - kn02_irq_base + 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	*csr = cached_kn02_csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static void ack_kn02_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	mask_kn02_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	iob();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static struct irq_chip kn02_irq_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	.name = "KN02-CSR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	.irq_ack = ack_kn02_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	.irq_mask = mask_kn02_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	.irq_mask_ack = ack_kn02_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	.irq_unmask = unmask_kn02_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) void __init init_kn02_irqs(int base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 						       KN02_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	/* Mask interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	cached_kn02_csr &= ~KN02_CSR_IOINTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	*csr = cached_kn02_csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	iob();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	for (i = base; i < base + KN02_IRQ_LINES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 		irq_set_chip_and_handler(i, &kn02_irq_type, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	kn02_irq_base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }