^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Bus error event handling code for DECstation/DECsystem 3100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * and 2100 (KN01) systems equipped with parity error detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * logic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2005 Maciej W. Rozycki
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/inst.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/irq_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/mipsregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/traps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/dec/kn01.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* CP0 hazard avoidance. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BARRIER \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) __asm__ __volatile__( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) ".set push\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ".set noreorder\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) "nop\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ".set pop\n\t")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Bits 7:0 of the Control Register are write-only -- the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * corresponding bits of the Status Register have a different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * meaning. Hence we use a cache. It speeds up things a bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * There is no default value -- it has to be initialized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u16 cached_kn01_csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static DEFINE_RAW_SPINLOCK(kn01_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static inline void dec_kn01_be_ack(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) raw_spin_lock_irqsave(&kn01_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *csr = cached_kn01_csr | KN01_CSR_MEMERR; /* Clear bus IRQ. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) iob();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) raw_spin_unlock_irqrestore(&kn01_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int dec_kn01_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) volatile u32 *kn01_erraddr = (void *)CKSEG1ADDR(KN01_SLOT_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) KN01_ERRADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static const char excstr[] = "exception";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static const char intstr[] = "interrupt";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static const char cpustr[] = "CPU";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static const char mreadstr[] = "memory read";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static const char readstr[] = "read";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static const char writestr[] = "write";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static const char timestr[] = "timeout";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static const char paritystr[] = "parity error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int data = regs->cp0_cause & 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned int __user *pc = (unsigned int __user *)regs->cp0_epc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ((regs->cp0_cause & CAUSEF_BD) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) union mips_instruction insn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned long entrylo, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) long asid, entryhi, vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) const char *kind, *agent, *cycle, *event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned long address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 erraddr = *kn01_erraddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int action = MIPS_BE_FATAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Ack ASAP, so that any subsequent errors get caught. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) dec_kn01_be_ack();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) kind = invoker ? intstr : excstr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) agent = cpustr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (invoker)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) address = erraddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Bloody hardware doesn't record the address for reads... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* This never faults. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) __get_user(insn.word, pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) vaddr = regs->regs[insn.i_format.rs] +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) insn.i_format.simmediate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) vaddr = (long)pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (KSEGX(vaddr) == CKSEG0 || KSEGX(vaddr) == CKSEG1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) address = CPHYSADDR(vaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Peek at what physical address the CPU used. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) asid = read_c0_entryhi();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) entryhi = asid & (PAGE_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) entryhi |= vaddr & ~(PAGE_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) write_c0_entryhi(entryhi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) BARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) tlb_probe();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* No need to check for presence. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) tlb_read();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) entrylo = read_c0_entrylo0();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) write_c0_entryhi(asid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) offset = vaddr & (PAGE_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) address = (entrylo & ~(PAGE_SIZE - 1)) | offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Treat low 256MB as memory, high -- as I/O. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (address < 0x10000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) cycle = mreadstr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) event = paritystr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) cycle = invoker ? writestr : readstr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) event = timestr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (is_fixup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) action = MIPS_BE_FIXUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (action != MIPS_BE_FIXUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) kind, agent, cycle, event, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return dec_kn01_be_backend(regs, is_fixup, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct pt_regs *regs = get_irq_regs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (!(*csr & KN01_CSR_MEMERR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return IRQ_NONE; /* Must have been video. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) action = dec_kn01_be_backend(regs, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (action == MIPS_BE_DISCARD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * FIXME: Find the affected processes and kill them, otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * we must die.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * The interrupt is asynchronously delivered thus EPC and RA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * may be irrelevant, but are printed for a reference.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) regs->cp0_epc, regs->regs[31]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) die("Unrecoverable bus error", regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) void __init dec_kn01_be_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) raw_spin_lock_irqsave(&kn01_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Preset write-only bits of the Control Register cache. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) cached_kn01_csr = *csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) cached_kn01_csr &= KN01_CSR_STATUS | KN01_CSR_PARDIS | KN01_CSR_TXDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) cached_kn01_csr |= KN01_CSR_LEDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Enable parity error detection. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) cached_kn01_csr &= ~KN01_CSR_PARDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) *csr = cached_kn01_csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) iob();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) raw_spin_unlock_irqrestore(&kn01_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* Clear any leftover errors from the firmware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) dec_kn01_be_ack();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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