Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * Register PCI controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Copyright (C) 1996, 1997, 2004, 05 by Ralf Baechle (ralf@linux-mips.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/gt64120.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) extern struct pci_ops gt64xxx_pci0_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static struct resource cobalt_mem_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	.start	= GT_DEF_PCI0_MEM0_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	.end	= GT_DEF_PCI0_MEM0_BASE + GT_DEF_PCI0_MEM0_SIZE - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	.name	= "PCI memory",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	.flags	= IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static struct resource cobalt_io_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	.start	= 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	.end	= 0xffffffUL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	.name	= "PCI I/O",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	.flags	= IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static struct pci_controller cobalt_pci_controller = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	.pci_ops	= &gt64xxx_pci0_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	.mem_resource	= &cobalt_mem_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	.io_resource	= &cobalt_io_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	.io_offset	= 0 - GT_DEF_PCI0_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	.io_map_base	= CKSEG1ADDR(GT_DEF_PCI0_IO_BASE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static int __init cobalt_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	register_pci_controller(&cobalt_pci_controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) arch_initcall(cobalt_pci_init);