^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * XHCI HCD glue for Cavium Octeon III SOCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2010-2017 Cavium Networks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/octeon/octeon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* USB Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) union cvm_usbdrd_uctl_ctl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) uint64_t u64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct cvm_usbdrd_uctl_ctl_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* 1 = BIST and set all USB RAMs to 0x0, 0 = BIST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) __BITFIELD_FIELD(uint64_t clear_bist:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* 1 = Start BIST and cleared by hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) __BITFIELD_FIELD(uint64_t start_bist:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Reference clock select for SuperSpeed and HighSpeed PLLs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * 0x0 = Both PLLs use DLMC_REF_CLK0 for reference clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * 0x1 = Both PLLs use DLMC_REF_CLK1 for reference clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * 0x2 = SuperSpeed PLL uses DLMC_REF_CLK0 for reference clock &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * HighSpeed PLL uses PLL_REF_CLK for reference clck
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * 0x3 = SuperSpeed PLL uses DLMC_REF_CLK1 for reference clock &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * HighSpeed PLL uses PLL_REF_CLK for reference clck
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) __BITFIELD_FIELD(uint64_t ref_clk_sel:2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* 1 = Spread-spectrum clock enable, 0 = SS clock disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) __BITFIELD_FIELD(uint64_t ssc_en:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Spread-spectrum clock modulation range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * 0x0 = -4980 ppm downspread
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * 0x1 = -4492 ppm downspread
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * 0x2 = -4003 ppm downspread
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * 0x3 - 0x7 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) __BITFIELD_FIELD(uint64_t ssc_range:3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Enable non-standard oscillator frequencies:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * [55:53] = modules -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * [52:47] = 2's complement push amount, 0 = Feature disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) __BITFIELD_FIELD(uint64_t ssc_ref_clk_sel:9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Reference clock multiplier for non-standard frequencies:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * 0x19 = 100MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * 0x28 = 125MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * 0x32 = 50MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Other Values = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) __BITFIELD_FIELD(uint64_t mpll_multiplier:7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Enable reference clock to prescaler for SuperSpeed functionality.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * Should always be set to "1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) __BITFIELD_FIELD(uint64_t ref_ssp_en:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Divide the reference clock by 2 before entering the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * REF_CLK_FSEL divider:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * If REF_CLK_SEL = 0x0 or 0x1, then only 0x0 is legal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * If REF_CLK_SEL = 0x2 or 0x3, then:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * 0x1 = DLMC_REF_CLK* is 125MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * 0x0 = DLMC_REF_CLK* is another supported frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) __BITFIELD_FIELD(uint64_t ref_clk_div2:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Select reference clock freqnuency for both PLL blocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * 0x27 = REF_CLK_SEL is 0x0 or 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * 0x07 = REF_CLK_SEL is 0x2 or 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) __BITFIELD_FIELD(uint64_t ref_clk_fsel:6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) __BITFIELD_FIELD(uint64_t reserved_31_31:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Controller clock enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) __BITFIELD_FIELD(uint64_t h_clk_en:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Select bypass input to controller clock divider:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * 0x0 = Use divided coprocessor clock from H_CLKDIV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * 0x1 = Use clock from GPIO pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __BITFIELD_FIELD(uint64_t h_clk_byp_sel:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Reset controller clock divider. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) __BITFIELD_FIELD(uint64_t h_clkdiv_rst:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) __BITFIELD_FIELD(uint64_t reserved_27_27:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Clock divider select:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * 0x0 = divide by 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * 0x1 = divide by 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * 0x2 = divide by 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * 0x3 = divide by 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * 0x4 = divide by 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * 0x5 = divide by 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * 0x6 = divide by 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * 0x7 = divide by 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) __BITFIELD_FIELD(uint64_t h_clkdiv_sel:3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) __BITFIELD_FIELD(uint64_t reserved_22_23:2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* USB3 port permanently attached: 0x0 = No, 0x1 = Yes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) __BITFIELD_FIELD(uint64_t usb3_port_perm_attach:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* USB2 port permanently attached: 0x0 = No, 0x1 = Yes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) __BITFIELD_FIELD(uint64_t usb2_port_perm_attach:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) __BITFIELD_FIELD(uint64_t reserved_19_19:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Disable SuperSpeed PHY: 0x0 = No, 0x1 = Yes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) __BITFIELD_FIELD(uint64_t usb3_port_disable:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) __BITFIELD_FIELD(uint64_t reserved_17_17:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Disable HighSpeed PHY: 0x0 = No, 0x1 = Yes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) __BITFIELD_FIELD(uint64_t usb2_port_disable:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) __BITFIELD_FIELD(uint64_t reserved_15_15:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Enable PHY SuperSpeed block power: 0x0 = No, 0x1 = Yes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) __BITFIELD_FIELD(uint64_t ss_power_en:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) __BITFIELD_FIELD(uint64_t reserved_13_13:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Enable PHY HighSpeed block power: 0x0 = No, 0x1 = Yes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) __BITFIELD_FIELD(uint64_t hs_power_en:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) __BITFIELD_FIELD(uint64_t reserved_5_11:7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Enable USB UCTL interface clock: 0xx = No, 0x1 = Yes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) __BITFIELD_FIELD(uint64_t csclk_en:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Controller mode: 0x0 = Host, 0x1 = Device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) __BITFIELD_FIELD(uint64_t drd_mode:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* PHY reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) __BITFIELD_FIELD(uint64_t uphy_rst:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Software reset UAHC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) __BITFIELD_FIELD(uint64_t uahc_rst:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Software resets UCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) __BITFIELD_FIELD(uint64_t uctl_rst:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ;)))))))))))))))))))))))))))))))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) } s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* UAHC Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) union cvm_usbdrd_uctl_host_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) uint64_t u64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct cvm_usbdrd_uctl_host_cfg_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) __BITFIELD_FIELD(uint64_t reserved_60_63:4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Indicates minimum value of all received BELT values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) __BITFIELD_FIELD(uint64_t host_current_belt:12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) __BITFIELD_FIELD(uint64_t reserved_38_47:10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* HS jitter adjustment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) __BITFIELD_FIELD(uint64_t fla:6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) __BITFIELD_FIELD(uint64_t reserved_29_31:3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Bus-master enable: 0x0 = Disabled (stall DMAs), 0x1 = enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) __BITFIELD_FIELD(uint64_t bme:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Overcurrent protection enable: 0x0 = unavailable, 0x1 = available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) __BITFIELD_FIELD(uint64_t oci_en:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Overcurrent sene selection:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * 0x0 = Overcurrent indication from off-chip is active-low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * 0x1 = Overcurrent indication from off-chip is active-high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) __BITFIELD_FIELD(uint64_t oci_active_high_en:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Port power control enable: 0x0 = unavailable, 0x1 = available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) __BITFIELD_FIELD(uint64_t ppc_en:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Port power control sense selection:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * 0x0 = Port power to off-chip is active-low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * 0x1 = Port power to off-chip is active-high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) __BITFIELD_FIELD(uint64_t ppc_active_high_en:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) __BITFIELD_FIELD(uint64_t reserved_0_23:24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ;)))))))))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) } s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* UCTL Shim Features Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) union cvm_usbdrd_uctl_shim_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) uint64_t u64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct cvm_usbdrd_uctl_shim_cfg_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Out-of-bound UAHC register access: 0 = read, 1 = write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) __BITFIELD_FIELD(uint64_t xs_ncb_oob_wrn:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) __BITFIELD_FIELD(uint64_t reserved_60_62:3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* SRCID error log for out-of-bound UAHC register access:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * [59:58] = chipID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * [57] = Request source: 0 = core, 1 = NCB-device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * [56:51] = Core/NCB-device number, [56] always 0 for NCB devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * [50:48] = SubID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) __BITFIELD_FIELD(uint64_t xs_ncb_oob_osrc:12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Error log for bad UAHC DMA access: 0 = Read log, 1 = Write log */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) __BITFIELD_FIELD(uint64_t xm_bad_dma_wrn:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) __BITFIELD_FIELD(uint64_t reserved_44_46:3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Encoded error type for bad UAHC DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) __BITFIELD_FIELD(uint64_t xm_bad_dma_type:4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) __BITFIELD_FIELD(uint64_t reserved_13_39:27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Select the IOI read command used by DMA accesses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) __BITFIELD_FIELD(uint64_t dma_read_cmd:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) __BITFIELD_FIELD(uint64_t reserved_10_11:2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Select endian format for DMA accesses to the L2c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * 0x0 = Little endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) *` 0x1 = Big endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * 0x2 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * 0x3 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) __BITFIELD_FIELD(uint64_t dma_endian_mode:2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) __BITFIELD_FIELD(uint64_t reserved_2_7:6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Select endian format for IOI CSR access to UAHC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * 0x0 = Little endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) *` 0x1 = Big endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * 0x2 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * 0x3 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) __BITFIELD_FIELD(uint64_t csr_endian_mode:2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ;))))))))))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) } s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define OCTEON_H_CLKDIV_SEL 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define OCTEON_MIN_H_CLK_RATE 150000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define OCTEON_MAX_H_CLK_RATE 300000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static DEFINE_MUTEX(dwc3_octeon_clocks_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static uint8_t clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static int dwc3_octeon_config_power(struct device *dev, u64 base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define UCTL_HOST_CFG 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) union cvm_usbdrd_uctl_host_cfg uctl_host_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) union cvmx_gpio_bit_cfgx gpio_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) uint32_t gpio_pwr[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int gpio, len, power_active_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int index = (base >> 24) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (of_find_property(node, "power", &len) != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (len == 12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) of_property_read_u32_array(node, "power", gpio_pwr, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) power_active_low = gpio_pwr[2] & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) gpio = gpio_pwr[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) } else if (len == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) of_property_read_u32_array(node, "power", gpio_pwr, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) power_active_low = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) gpio = gpio_pwr[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) dev_err(dev, "dwc3 controller clock init failure.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if ((OCTEON_IS_MODEL(OCTEON_CN73XX) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) OCTEON_IS_MODEL(OCTEON_CNF75XX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) && gpio <= 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) gpio_bit.s.tx_oe = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) } else if (gpio <= 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) gpio_bit.s.tx_oe = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) gpio_bit.s.tx_oe = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(gpio), gpio_bit.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* Enable XHCI power control and set if active high or low. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) uctl_host_cfg.s.ppc_en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) uctl_host_cfg.s.ppc_active_high_en = !power_active_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Disable XHCI power control and set if active high. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) uctl_host_cfg.s.ppc_en = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) uctl_host_cfg.s.ppc_active_high_en = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dev_warn(dev, "dwc3 controller clock init failure.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) union cvm_usbdrd_uctl_ctl uctl_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int ref_clk_sel = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u64 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u32 clock_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int mpll_mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u64 h_clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u64 uctl_ctl_reg = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (dev->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) const char *ss_clock_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) const char *hs_clock_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) i = of_property_read_u32(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) "refclk-frequency", &clock_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) pr_err("No UCTL \"refclk-frequency\"\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) i = of_property_read_string(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) "refclk-type-ss", &ss_clock_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) pr_err("No UCTL \"refclk-type-ss\"\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) i = of_property_read_string(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) "refclk-type-hs", &hs_clock_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) pr_err("No UCTL \"refclk-type-hs\"\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (strcmp(hs_clock_type, "dlmc_ref_clk0") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ref_clk_sel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) else if (strcmp(hs_clock_type, "pll_ref_clk") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ref_clk_sel = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) pr_err("Invalid HS clock type %s, using pll_ref_clk instead\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) hs_clock_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) } else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ref_clk_sel = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) else if (strcmp(hs_clock_type, "pll_ref_clk") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ref_clk_sel = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) pr_err("Invalid HS clock type %s, using pll_ref_clk instead\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) hs_clock_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ref_clk_sel = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) pr_err("Invalid SS clock type %s, using dlmc_ref_clk0 instead\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ss_clock_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if ((ref_clk_sel == 0 || ref_clk_sel == 1) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) (clock_rate != 100000000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) pr_err("Invalid UCTL clock rate of %u, using 100000000 instead\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) clock_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) pr_err("No USB UCTL device node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * Step 1: Wait for all voltages to be stable...that surely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * happened before starting the kernel. SKIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* Step 2: Select GPIO for overcurrent indication, if desired. SKIP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* Step 3: Assert all resets. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) uctl_ctl.s.uphy_rst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) uctl_ctl.s.uahc_rst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) uctl_ctl.s.uctl_rst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Step 4a: Reset the clock dividers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) uctl_ctl.s.h_clkdiv_rst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* Step 4b: Select controller clock frequency. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) for (div = 0; div < OCTEON_H_CLKDIV_SEL; div++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) h_clk_rate = octeon_get_io_clock_rate() / clk_div[div];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (h_clk_rate <= OCTEON_MAX_H_CLK_RATE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) h_clk_rate >= OCTEON_MIN_H_CLK_RATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) uctl_ctl.s.h_clkdiv_sel = div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) uctl_ctl.s.h_clk_en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if ((div != uctl_ctl.s.h_clkdiv_sel) || (!uctl_ctl.s.h_clk_en)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) dev_err(dev, "dwc3 controller clock init failure.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* Step 4c: Deassert the controller clock divider reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) uctl_ctl.s.h_clkdiv_rst = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* Step 5a: Reference clock configuration. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) uctl_ctl.s.ref_clk_sel = ref_clk_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) uctl_ctl.s.ref_clk_fsel = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) uctl_ctl.s.ref_clk_div2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) switch (clock_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dev_err(dev, "Invalid ref_clk %u, using 100000000 instead\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) clock_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) case 100000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) mpll_mul = 0x19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (ref_clk_sel < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) uctl_ctl.s.ref_clk_fsel = 0x27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) case 50000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) mpll_mul = 0x32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) case 125000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) mpll_mul = 0x28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) uctl_ctl.s.mpll_multiplier = mpll_mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* Step 5b: Configure and enable spread-spectrum for SuperSpeed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) uctl_ctl.s.ssc_en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Step 5c: Enable SuperSpeed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) uctl_ctl.s.ref_ssp_en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Step 5d: Cofngiure PHYs. SKIP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* Step 6a & 6b: Power up PHYs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) uctl_ctl.s.hs_power_en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) uctl_ctl.s.ss_power_en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* Step 7: Wait 10 controller-clock cycles to take effect. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* Step 8a: Deassert UCTL reset signal. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) uctl_ctl.s.uctl_rst = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* Step 8b: Wait 10 controller-clock cycles. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* Steo 8c: Setup power-power control. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (dwc3_octeon_config_power(dev, base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) dev_err(dev, "Error configuring power.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* Step 8d: Deassert UAHC reset signal. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) uctl_ctl.s.uahc_rst = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* Step 8e: Wait 10 controller-clock cycles. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* Step 9: Enable conditional coprocessor clock of UCTL. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) uctl_ctl.s.csclk_en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /*Step 10: Set for host mode only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) uctl_ctl.s.drd_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static void __init dwc3_octeon_set_endian_mode(u64 base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define UCTL_SHIM_CFG 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) union cvm_usbdrd_uctl_shim_cfg shim_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) shim_cfg.u64 = cvmx_read_csr(base + UCTL_SHIM_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) shim_cfg.s.dma_endian_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) shim_cfg.s.csr_endian_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) shim_cfg.s.dma_endian_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) shim_cfg.s.csr_endian_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) cvmx_write_csr(base + UCTL_SHIM_CFG, shim_cfg.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define CVMX_USBDRDX_UCTL_CTL(index) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) (CVMX_ADD_IO_SEG(0x0001180068000000ull) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ((index & 1) * 0x1000000ull))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static void __init dwc3_octeon_phy_reset(u64 base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) union cvm_usbdrd_uctl_ctl uctl_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) int index = (base >> 24) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) uctl_ctl.u64 = cvmx_read_csr(CVMX_USBDRDX_UCTL_CTL(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) uctl_ctl.s.uphy_rst = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) cvmx_write_csr(CVMX_USBDRDX_UCTL_CTL(index), uctl_ctl.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static int __init dwc3_octeon_device_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) const char compat_node_name[] = "cavium,octeon-7130-usb-uctl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * There should only be three universal controllers, "uctl"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * in the device tree. Two USB and a SATA, which we ignore.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) node = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) node = of_find_node_by_name(node, "uctl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (!node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (of_device_is_compatible(node, compat_node_name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) pdev = of_find_device_by_node(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (!pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (res == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) put_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) dev_err(&pdev->dev, "No memory resources\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * The code below maps in the registers necessary for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * setting up the clocks and reseting PHYs. We must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * release the resources so the dwc3 subsystem doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * know the difference.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (IS_ERR(base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) put_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) mutex_lock(&dwc3_octeon_clocks_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) dwc3_octeon_clocks_start(&pdev->dev, (u64)base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) dwc3_octeon_set_endian_mode((u64)base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) dwc3_octeon_phy_reset((u64)base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) dev_info(&pdev->dev, "clocks initialized.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) mutex_unlock(&dwc3_octeon_clocks_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) devm_iounmap(&pdev->dev, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) devm_release_mem_region(&pdev->dev, res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) put_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) } while (node != NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) device_initcall(dwc3_octeon_device_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) MODULE_AUTHOR("David Daney <david.daney@cavium.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) MODULE_DESCRIPTION("USB driver for OCTEON III SoC");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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