^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /***********************license start***************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Author: Cavium Networks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Contact: support@caviumnetworks.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This file is part of the OCTEON SDK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2003-2017 Cavium, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This file is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * it under the terms of the GNU General Public License, Version 2, as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * This file is distributed in the hope that it will be useful, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * NONINFRINGEMENT. See the GNU General Public License for more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * along with this file; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * or visit http://www.gnu.org/licenses/.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * This file may also be available under a different license from Cavium.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Contact Cavium Networks for more information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) ***********************license end**************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Implementation of the Level 2 Cache (L2C) control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * measurement, and debugging facilities.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/irqflags.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/octeon/cvmx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/octeon/cvmx-l2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/octeon/cvmx-spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * This spinlock is used internally to ensure that only one core is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * performing certain L2 operations at a time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * NOTE: This only protects calls from within a single application -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * if multiple applications or operating systems are running, then it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * is up to the user program to coordinate between them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static cvmx_spinlock_t cvmx_l2c_spinlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int cvmx_l2c_get_core_way_partition(uint32_t core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) uint32_t field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Validate the core number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (core >= cvmx_octeon_num_cores())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (OCTEON_IS_MODEL(OCTEON_CN63XX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return cvmx_read_csr(CVMX_L2C_WPAR_PPX(core)) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * Use the lower two bits of the coreNumber to determine the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * bit offset of the UMSK[] field in the L2C_SPAR register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) field = (core & 0x3) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Return the UMSK[] field from the appropriate L2C_SPAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * register based on the coreNumber.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) switch (core & 0xC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) case 0x0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return (cvmx_read_csr(CVMX_L2C_SPAR0) & (0xFF << field)) >> field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) case 0x4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return (cvmx_read_csr(CVMX_L2C_SPAR1) & (0xFF << field)) >> field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) case 0x8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return (cvmx_read_csr(CVMX_L2C_SPAR2) & (0xFF << field)) >> field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) case 0xC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return (cvmx_read_csr(CVMX_L2C_SPAR3) & (0xFF << field)) >> field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) uint32_t field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) uint32_t valid_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) valid_mask = (0x1 << cvmx_l2c_get_num_assoc()) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) mask &= valid_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* A UMSK setting which blocks all L2C Ways is an error on some chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (mask == valid_mask && !OCTEON_IS_MODEL(OCTEON_CN63XX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Validate the core number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (core >= cvmx_octeon_num_cores())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) cvmx_write_csr(CVMX_L2C_WPAR_PPX(core), mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * Use the lower two bits of core to determine the bit offset of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * UMSK[] field in the L2C_SPAR register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) field = (core & 0x3) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * Assign the new mask setting to the UMSK[] field in the appropriate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * L2C_SPAR register based on the core_num.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) switch (core & 0xC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) case 0x0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) cvmx_write_csr(CVMX_L2C_SPAR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) (cvmx_read_csr(CVMX_L2C_SPAR0) & ~(0xFF << field)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) mask << field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) case 0x4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) cvmx_write_csr(CVMX_L2C_SPAR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) (cvmx_read_csr(CVMX_L2C_SPAR1) & ~(0xFF << field)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) mask << field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) case 0x8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) cvmx_write_csr(CVMX_L2C_SPAR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) (cvmx_read_csr(CVMX_L2C_SPAR2) & ~(0xFF << field)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) mask << field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) case 0xC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) cvmx_write_csr(CVMX_L2C_SPAR3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) (cvmx_read_csr(CVMX_L2C_SPAR3) & ~(0xFF << field)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) mask << field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int cvmx_l2c_set_hw_way_partition(uint32_t mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) uint32_t valid_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) valid_mask = (0x1 << cvmx_l2c_get_num_assoc()) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) mask &= valid_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* A UMSK setting which blocks all L2C Ways is an error on some chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (mask == valid_mask && !OCTEON_IS_MODEL(OCTEON_CN63XX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (OCTEON_IS_MODEL(OCTEON_CN63XX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) cvmx_write_csr(CVMX_L2C_WPAR_IOBX(0), mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) cvmx_write_csr(CVMX_L2C_SPAR4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) (cvmx_read_csr(CVMX_L2C_SPAR4) & ~0xFF) | mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int cvmx_l2c_get_hw_way_partition(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (OCTEON_IS_MODEL(OCTEON_CN63XX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return cvmx_read_csr(CVMX_L2C_WPAR_IOBX(0)) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return cvmx_read_csr(CVMX_L2C_SPAR4) & (0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) void cvmx_l2c_config_perf(uint32_t counter, enum cvmx_l2c_event event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) uint32_t clear_on_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) union cvmx_l2c_pfctl pfctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) pfctl.u64 = cvmx_read_csr(CVMX_L2C_PFCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) switch (counter) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) pfctl.s.cnt0sel = event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) pfctl.s.cnt0ena = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) pfctl.s.cnt0rdclr = clear_on_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) pfctl.s.cnt1sel = event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) pfctl.s.cnt1ena = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) pfctl.s.cnt1rdclr = clear_on_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) pfctl.s.cnt2sel = event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) pfctl.s.cnt2ena = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) pfctl.s.cnt2rdclr = clear_on_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) pfctl.s.cnt3sel = event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) pfctl.s.cnt3ena = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pfctl.s.cnt3rdclr = clear_on_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) cvmx_write_csr(CVMX_L2C_PFCTL, pfctl.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) union cvmx_l2c_tadx_prf l2c_tadx_prf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int tad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) cvmx_dprintf("L2C performance counter events are different for this chip, mapping 'event' to cvmx_l2c_tad_event_t\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (clear_on_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) cvmx_dprintf("L2C counters don't support clear on read for this chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) l2c_tadx_prf.u64 = cvmx_read_csr(CVMX_L2C_TADX_PRF(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) switch (counter) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) l2c_tadx_prf.s.cnt0sel = event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) l2c_tadx_prf.s.cnt1sel = event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) l2c_tadx_prf.s.cnt2sel = event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) l2c_tadx_prf.s.cnt3sel = event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) for (tad = 0; tad < CVMX_L2C_TADS; tad++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) cvmx_write_csr(CVMX_L2C_TADX_PRF(tad),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) l2c_tadx_prf.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) uint64_t cvmx_l2c_read_perf(uint32_t counter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) switch (counter) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return cvmx_read_csr(CVMX_L2C_PFC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) uint64_t counter = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int tad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) for (tad = 0; tad < CVMX_L2C_TADS; tad++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) counter += cvmx_read_csr(CVMX_L2C_TADX_PFC0(tad));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return cvmx_read_csr(CVMX_L2C_PFC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) uint64_t counter = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int tad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) for (tad = 0; tad < CVMX_L2C_TADS; tad++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) counter += cvmx_read_csr(CVMX_L2C_TADX_PFC1(tad));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return cvmx_read_csr(CVMX_L2C_PFC2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) uint64_t counter = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int tad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) for (tad = 0; tad < CVMX_L2C_TADS; tad++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) counter += cvmx_read_csr(CVMX_L2C_TADX_PFC2(tad));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return cvmx_read_csr(CVMX_L2C_PFC3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) uint64_t counter = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int tad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) for (tad = 0; tad < CVMX_L2C_TADS; tad++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) counter += cvmx_read_csr(CVMX_L2C_TADX_PFC3(tad));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * @INTERNAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * Helper function use to fault in cache lines for L2 cache locking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * @addr: Address of base of memory region to read into L2 cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * @len: Length (in bytes) of region to fault in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static void fault_in(uint64_t addr, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) char *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * Adjust addr and length so we get all cache lines even for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * small ranges spanning two cache lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) len += addr & CVMX_CACHE_LINE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) addr &= ~CVMX_CACHE_LINE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ptr = cvmx_phys_to_ptr(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * Invalidate L1 cache to make sure all loads result in data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * being in L2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) CVMX_DCACHE_INVALIDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) while (len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) READ_ONCE(*ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) len -= CVMX_CACHE_LINE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ptr += CVMX_CACHE_LINE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int cvmx_l2c_lock_line(uint64_t addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) int shift = CVMX_L2C_TAG_ADDR_ALIAS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) uint64_t assoc = cvmx_l2c_get_num_assoc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) uint64_t tag = addr >> shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) uint64_t index = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, cvmx_l2c_address_to_index(addr) << CVMX_L2C_IDX_ADDR_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) uint64_t way;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) union cvmx_l2c_tadx_tag l2c_tadx_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) CVMX_CACHE_LCKL2(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, addr), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* Make sure we were able to lock the line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) for (way = 0; way < assoc; way++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) CVMX_CACHE_LTGL2I(index | (way << shift), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* make sure CVMX_L2C_TADX_TAG is updated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) CVMX_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) l2c_tadx_tag.u64 = cvmx_read_csr(CVMX_L2C_TADX_TAG(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (l2c_tadx_tag.s.valid && l2c_tadx_tag.s.tag == tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* Check if a valid line is found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (way >= assoc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* cvmx_dprintf("ERROR: cvmx_l2c_lock_line: line not found for locking at 0x%llx address\n", (unsigned long long)addr); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Check if lock bit is not set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (!l2c_tadx_tag.s.lock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* cvmx_dprintf("ERROR: cvmx_l2c_lock_line: Not able to lock at 0x%llx address\n", (unsigned long long)addr); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return way;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) union cvmx_l2c_dbg l2cdbg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) union cvmx_l2c_lckbase lckbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) union cvmx_l2c_lckoff lckoff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) union cvmx_l2t_err l2t_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) cvmx_spinlock_lock(&cvmx_l2c_spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) l2cdbg.u64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) lckbase.u64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) lckoff.u64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* Clear l2t error bits if set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) l2t_err.s.lckerr = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) l2t_err.s.lckerr2 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) cvmx_write_csr(CVMX_L2T_ERR, l2t_err.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) addr &= ~CVMX_CACHE_LINE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Set this core as debug core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) l2cdbg.s.ppnum = cvmx_get_core_num();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) CVMX_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) cvmx_read_csr(CVMX_L2C_DBG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) lckoff.s.lck_offset = 0; /* Only lock 1 line at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) cvmx_write_csr(CVMX_L2C_LCKOFF, lckoff.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) cvmx_read_csr(CVMX_L2C_LCKOFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (((union cvmx_l2c_cfg)(cvmx_read_csr(CVMX_L2C_CFG))).s.idxalias) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) int alias_shift = CVMX_L2C_IDX_ADDR_SHIFT + 2 * CVMX_L2_SET_BITS - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) uint64_t addr_tmp = addr ^ (addr & ((1 << alias_shift) - 1)) >> CVMX_L2_SET_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) lckbase.s.lck_base = addr_tmp >> 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) lckbase.s.lck_base = addr >> 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) lckbase.s.lck_ena = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Make sure it gets there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) cvmx_read_csr(CVMX_L2C_LCKBASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) fault_in(addr, CVMX_CACHE_LINE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) lckbase.s.lck_ena = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Make sure it gets there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) cvmx_read_csr(CVMX_L2C_LCKBASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* Stop being debug core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) cvmx_write_csr(CVMX_L2C_DBG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) cvmx_read_csr(CVMX_L2C_DBG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (l2t_err.s.lckerr || l2t_err.s.lckerr2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) retval = 1; /* We were unable to lock the line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* Round start/end to cache line boundaries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) len += start & CVMX_CACHE_LINE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) start &= ~CVMX_CACHE_LINE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) len = (len + CVMX_CACHE_LINE_MASK) & ~CVMX_CACHE_LINE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) while (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) retval += cvmx_l2c_lock_line(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) start += CVMX_CACHE_LINE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) len -= CVMX_CACHE_LINE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) void cvmx_l2c_flush(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) uint64_t assoc, set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) uint64_t n_assoc, n_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) n_set = cvmx_l2c_get_num_sets();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) n_assoc = cvmx_l2c_get_num_assoc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) uint64_t address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* These may look like constants, but they aren't... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) int assoc_shift = CVMX_L2C_TAG_ADDR_ALIAS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int set_shift = CVMX_L2C_IDX_ADDR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) for (set = 0; set < n_set; set++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) for (assoc = 0; assoc < n_assoc; assoc++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) (assoc << assoc_shift) | (set << set_shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) CVMX_CACHE_WBIL2I(address, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) for (set = 0; set < n_set; set++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) for (assoc = 0; assoc < n_assoc; assoc++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) cvmx_l2c_flush_line(assoc, set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) int cvmx_l2c_unlock_line(uint64_t address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int assoc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) union cvmx_l2c_tag tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) uint32_t tag_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) uint32_t index = cvmx_l2c_address_to_index(address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) tag_addr = ((address >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) & ((1 << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * For 63XX, we can flush a line by using the physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * address directly, so finding the cache line used by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * the address is only required to provide the proper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * return value for the function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) for (assoc = 0; assoc < CVMX_L2_ASSOC; assoc++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) tag = cvmx_l2c_get_tag(assoc, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (tag.s.V && (tag.s.addr == tag_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) CVMX_CACHE_WBIL2(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, address), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return tag.s.L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) int assoc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) union cvmx_l2c_tag tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) uint32_t tag_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) uint32_t index = cvmx_l2c_address_to_index(address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* Compute portion of address that is stored in tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) tag_addr = ((address >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) & ((1 << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) for (assoc = 0; assoc < CVMX_L2_ASSOC; assoc++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) tag = cvmx_l2c_get_tag(assoc, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (tag.s.V && (tag.s.addr == tag_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) cvmx_l2c_flush_line(assoc, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return tag.s.L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) int num_unlocked = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* Round start/end to cache line boundaries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) len += start & CVMX_CACHE_LINE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) start &= ~CVMX_CACHE_LINE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) len = (len + CVMX_CACHE_LINE_MASK) & ~CVMX_CACHE_LINE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) while (len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) num_unlocked += cvmx_l2c_unlock_line(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) start += CVMX_CACHE_LINE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) len -= CVMX_CACHE_LINE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return num_unlocked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * Internal l2c tag types. These are converted to a generic structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * that can be used on all chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) union __cvmx_l2c_tag {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) uint64_t u64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct cvmx_l2c_tag_cn50xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) __BITFIELD_FIELD(uint64_t reserved:40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) __BITFIELD_FIELD(uint64_t V:1, /* Line valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) __BITFIELD_FIELD(uint64_t D:1, /* Line dirty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) __BITFIELD_FIELD(uint64_t L:1, /* Line locked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) __BITFIELD_FIELD(uint64_t U:1, /* Use, LRU eviction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) __BITFIELD_FIELD(uint64_t addr:20, /* Phys addr (33..14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ;))))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) } cn50xx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct cvmx_l2c_tag_cn30xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) __BITFIELD_FIELD(uint64_t reserved:41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) __BITFIELD_FIELD(uint64_t V:1, /* Line valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) __BITFIELD_FIELD(uint64_t D:1, /* Line dirty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) __BITFIELD_FIELD(uint64_t L:1, /* Line locked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) __BITFIELD_FIELD(uint64_t U:1, /* Use, LRU eviction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) __BITFIELD_FIELD(uint64_t addr:19, /* Phys addr (33..15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ;))))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) } cn30xx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct cvmx_l2c_tag_cn31xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) __BITFIELD_FIELD(uint64_t reserved:42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) __BITFIELD_FIELD(uint64_t V:1, /* Line valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) __BITFIELD_FIELD(uint64_t D:1, /* Line dirty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) __BITFIELD_FIELD(uint64_t L:1, /* Line locked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) __BITFIELD_FIELD(uint64_t U:1, /* Use, LRU eviction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) __BITFIELD_FIELD(uint64_t addr:18, /* Phys addr (33..16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ;))))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) } cn31xx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct cvmx_l2c_tag_cn38xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) __BITFIELD_FIELD(uint64_t reserved:43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) __BITFIELD_FIELD(uint64_t V:1, /* Line valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) __BITFIELD_FIELD(uint64_t D:1, /* Line dirty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) __BITFIELD_FIELD(uint64_t L:1, /* Line locked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) __BITFIELD_FIELD(uint64_t U:1, /* Use, LRU eviction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) __BITFIELD_FIELD(uint64_t addr:17, /* Phys addr (33..17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ;))))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) } cn38xx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct cvmx_l2c_tag_cn58xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) __BITFIELD_FIELD(uint64_t reserved:44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) __BITFIELD_FIELD(uint64_t V:1, /* Line valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) __BITFIELD_FIELD(uint64_t D:1, /* Line dirty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) __BITFIELD_FIELD(uint64_t L:1, /* Line locked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) __BITFIELD_FIELD(uint64_t U:1, /* Use, LRU eviction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) __BITFIELD_FIELD(uint64_t addr:16, /* Phys addr (33..18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ;))))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) } cn58xx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct cvmx_l2c_tag_cn58xx cn56xx; /* 2048 sets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct cvmx_l2c_tag_cn31xx cn52xx; /* 512 sets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * @INTERNAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * Function to read a L2C tag. This code make the current core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * the 'debug core' for the L2. This code must only be executed by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * 1 core at a time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * @assoc: Association (way) of the tag to dump
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * @index: Index of the cacheline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * Returns The Octeon model specific tag structure. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * translated by a wrapper function to a generic form that is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * easier for applications to use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static union __cvmx_l2c_tag __read_l2_tag(uint64_t assoc, uint64_t index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) uint64_t debug_tag_addr = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, (index << 7) + 96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) uint64_t core = cvmx_get_core_num();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) union __cvmx_l2c_tag tag_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) uint64_t dbg_addr = CVMX_L2C_DBG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) union cvmx_l2c_dbg debug_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) debug_val.u64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * For low core count parts, the core number is always small
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * enough to stay in the correct field and not set any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * reserved bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) debug_val.s.ppnum = core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) debug_val.s.l2t = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) debug_val.s.set = assoc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * Make sure core is quiet (no prefetches, etc.) before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * entering debug mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) CVMX_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* Flush L1 to make sure debug load misses L1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) CVMX_DCACHE_INVALIDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * The following must be done in assembly as when in debug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * mode all data loads from L2 return special debug data, not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * normal memory contents. Also, interrupts must be disabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * since if an interrupt occurs while in debug mode the ISR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * will get debug data from all its memory * reads instead of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * the contents of memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) asm volatile (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) ".set push\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ".set mips64\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) ".set noreorder\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) "sd %[dbg_val], 0(%[dbg_addr])\n\t" /* Enter debug mode, wait for store */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) "ld $0, 0(%[dbg_addr])\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) "ld %[tag_val], 0(%[tag_addr])\n\t" /* Read L2C tag data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) "sd $0, 0(%[dbg_addr])\n\t" /* Exit debug mode, wait for store */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) "ld $0, 0(%[dbg_addr])\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) "cache 9, 0($0)\n\t" /* Invalidate dcache to discard debug data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) ".set pop"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) : [tag_val] "=r" (tag_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) : [dbg_addr] "r" (dbg_addr), [dbg_val] "r" (debug_val), [tag_addr] "r" (debug_tag_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return tag_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) union cvmx_l2c_tag tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) tag.u64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if ((int)association >= cvmx_l2c_get_num_assoc()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) cvmx_dprintf("ERROR: cvmx_l2c_get_tag association out of range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if ((int)index >= cvmx_l2c_get_num_sets()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) cvmx_dprintf("ERROR: cvmx_l2c_get_tag index out of range (arg: %d, max: %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) (int)index, cvmx_l2c_get_num_sets());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) union cvmx_l2c_tadx_tag l2c_tadx_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) uint64_t address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) (association << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) (index << CVMX_L2C_IDX_ADDR_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * Use L2 cache Index load tag cache instruction, as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * hardware loads the virtual tag for the L2 cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * block with the contents of L2C_TAD0_TAG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) CVMX_CACHE_LTGL2I(address, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) CVMX_SYNC; /* make sure CVMX_L2C_TADX_TAG is updated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) l2c_tadx_tag.u64 = cvmx_read_csr(CVMX_L2C_TADX_TAG(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) tag.s.V = l2c_tadx_tag.s.valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) tag.s.D = l2c_tadx_tag.s.dirty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) tag.s.L = l2c_tadx_tag.s.lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) tag.s.U = l2c_tadx_tag.s.use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) tag.s.addr = l2c_tadx_tag.s.tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) union __cvmx_l2c_tag tmp_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* __read_l2_tag is intended for internal use only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) tmp_tag = __read_l2_tag(association, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * Convert all tag structure types to generic version,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * as it can represent all models.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) tag.s.V = tmp_tag.cn58xx.V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) tag.s.D = tmp_tag.cn58xx.D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) tag.s.L = tmp_tag.cn58xx.L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) tag.s.U = tmp_tag.cn58xx.U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) tag.s.addr = tmp_tag.cn58xx.addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) } else if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) tag.s.V = tmp_tag.cn38xx.V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) tag.s.D = tmp_tag.cn38xx.D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) tag.s.L = tmp_tag.cn38xx.L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) tag.s.U = tmp_tag.cn38xx.U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) tag.s.addr = tmp_tag.cn38xx.addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) } else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) tag.s.V = tmp_tag.cn31xx.V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) tag.s.D = tmp_tag.cn31xx.D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) tag.s.L = tmp_tag.cn31xx.L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) tag.s.U = tmp_tag.cn31xx.U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) tag.s.addr = tmp_tag.cn31xx.addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) } else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) tag.s.V = tmp_tag.cn30xx.V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) tag.s.D = tmp_tag.cn30xx.D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) tag.s.L = tmp_tag.cn30xx.L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) tag.s.U = tmp_tag.cn30xx.U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) tag.s.addr = tmp_tag.cn30xx.addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) } else if (OCTEON_IS_MODEL(OCTEON_CN50XX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) tag.s.V = tmp_tag.cn50xx.V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) tag.s.D = tmp_tag.cn50xx.D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) tag.s.L = tmp_tag.cn50xx.L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) tag.s.U = tmp_tag.cn50xx.U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) tag.s.addr = tmp_tag.cn50xx.addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) uint32_t cvmx_l2c_address_to_index(uint64_t addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) uint64_t idx = addr >> CVMX_L2C_IDX_ADDR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) int indxalias = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) union cvmx_l2c_ctl l2c_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) l2c_ctl.u64 = cvmx_read_csr(CVMX_L2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) indxalias = !l2c_ctl.s.disidxalias;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) union cvmx_l2c_cfg l2c_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) indxalias = l2c_cfg.s.idxalias;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (indxalias) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) uint32_t a_14_12 = (idx / (CVMX_L2C_MEMBANK_SELECT_SIZE/(1<<CVMX_L2C_IDX_ADDR_SHIFT))) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) idx ^= idx / cvmx_l2c_get_num_sets();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) idx ^= a_14_12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) idx ^= ((addr & CVMX_L2C_ALIAS_MASK) >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) idx &= CVMX_L2C_IDX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) int cvmx_l2c_get_cache_size_bytes(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return cvmx_l2c_get_num_sets() * cvmx_l2c_get_num_assoc() *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) CVMX_CACHE_LINE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * Return log base 2 of the number of sets in the L2 cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * Returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) int cvmx_l2c_get_set_bits(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) int l2_set_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) l2_set_bits = 11; /* 2048 sets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) else if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) l2_set_bits = 10; /* 1024 sets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) l2_set_bits = 9; /* 512 sets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) else if (OCTEON_IS_MODEL(OCTEON_CN30XX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) l2_set_bits = 8; /* 256 sets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) else if (OCTEON_IS_MODEL(OCTEON_CN50XX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) l2_set_bits = 7; /* 128 sets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) l2_set_bits = 11; /* 2048 sets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return l2_set_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /* Return the number of sets in the L2 Cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) int cvmx_l2c_get_num_sets(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return 1 << cvmx_l2c_get_set_bits();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /* Return the number of associations in the L2 Cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) int cvmx_l2c_get_num_assoc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) int l2_assoc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (OCTEON_IS_MODEL(OCTEON_CN56XX) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) OCTEON_IS_MODEL(OCTEON_CN52XX) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) OCTEON_IS_MODEL(OCTEON_CN58XX) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) OCTEON_IS_MODEL(OCTEON_CN50XX) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) OCTEON_IS_MODEL(OCTEON_CN38XX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) l2_assoc = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) else if (OCTEON_IS_MODEL(OCTEON_CN63XX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) l2_assoc = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) else if (OCTEON_IS_MODEL(OCTEON_CN31XX) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) OCTEON_IS_MODEL(OCTEON_CN30XX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) l2_assoc = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) l2_assoc = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /* Check to see if part of the cache is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) union cvmx_mio_fus_dat3 mio_fus_dat3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) mio_fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) * cvmx_mio_fus_dat3.s.l2c_crip fuses map as follows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) * <2> will be not used for 63xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * <1> disables 1/2 ways
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * <0> disables 1/4 ways
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) * They are cumulative, so for 63xx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) * <1> <0>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) * 0 0 16-way 2MB cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) * 0 1 12-way 1.5MB cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) * 1 0 8-way 1MB cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) * 1 1 4-way 512KB cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (mio_fus_dat3.s.l2c_crip == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) l2_assoc = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) else if (mio_fus_dat3.s.l2c_crip == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) l2_assoc = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) else if (mio_fus_dat3.s.l2c_crip == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) l2_assoc = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) uint64_t l2d_fus3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) l2d_fus3 = cvmx_read_csr(CVMX_L2D_FUS3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) * Using shifts here, as bit position names are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) * different for each model but they all mean the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) * same.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if ((l2d_fus3 >> 35) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) l2_assoc = l2_assoc >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) else if ((l2d_fus3 >> 34) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) l2_assoc = l2_assoc >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return l2_assoc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * Flush a line from the L2 cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * This should only be called from one core at a time, as this routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * sets the core to the 'debug' core in order to flush the line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) * @assoc: Association (or way) to flush
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * @index: Index to flush
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /* Check the range of the index. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (index > (uint32_t)cvmx_l2c_get_num_sets()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) cvmx_dprintf("ERROR: cvmx_l2c_flush_line index out of range.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /* Check the range of association. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (assoc > (uint32_t)cvmx_l2c_get_num_assoc()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) cvmx_dprintf("ERROR: cvmx_l2c_flush_line association out of range.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) uint64_t address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* Create the address based on index and association.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) * Bits<20:17> select the way of the cache block involved in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * the operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) * Bits<16:7> of the effect address select the index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) (assoc << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) (index << CVMX_L2C_IDX_ADDR_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) CVMX_CACHE_WBIL2I(address, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) union cvmx_l2c_dbg l2cdbg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) l2cdbg.u64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (!OCTEON_IS_MODEL(OCTEON_CN30XX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) l2cdbg.s.ppnum = cvmx_get_core_num();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) l2cdbg.s.finv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) l2cdbg.s.set = assoc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) cvmx_spinlock_lock(&cvmx_l2c_spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) * Enter debug mode, and make sure all other writes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * complete before we enter debug mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) CVMX_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) cvmx_read_csr(CVMX_L2C_DBG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) CVMX_PREPARE_FOR_STORE(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) index * CVMX_CACHE_LINE_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) /* Exit debug mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) CVMX_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) cvmx_write_csr(CVMX_L2C_DBG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) cvmx_read_csr(CVMX_L2C_DBG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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